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5T93GL161PFGI

Description
IC CLK BUFFER 2:16 450MHZ 64TQFP
Categorysemiconductor    Analog mixed-signal IC   
File Size804KB,20 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance
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5T93GL161PFGI Overview

IC CLK BUFFER 2:16 450MHZ 64TQFP

5T93GL161PFGI Parametric

Parameter NameAttribute value
typefanout buffer (allocation), multiplexer
Number of circuits1
Ratio - Input:Output2:16
Differential - Input:OutputYes Yes
enterCML,eHSTL,HSTL,LVDS,LVPECL,LVTTL
outputLVDS
Frequency - maximum450MHz
Voltage - Power2.3 V ~ 2.7 V
Operating temperature-40°C ~ 85°C
Installation typesurface mount
Package/casing64-LQFP
Supplier device packaging64-TQFP(10x10)
2.5V LVDS, 1:16 GLITCHLESS CLOCK BUFFER
TERABUFFER™ II
General Description
The IDT5T93GL161 2.5V differential clock buffer is a
user-selectable differential input to sixteen LVDS outputs. The
fanout from a differential input to sixteen LVDS outputs reduces
loading on the preceding driver and provides an efficient clock
distribution network. The IDT5T93GL161 can act as a translator
from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V
/ 2.5V LVTTL input can also be used to translate to LVDS outputs.
The redundant input capability allows for
a
glitchless change-over
from a primary clock source to a secondary clock source.
Selectable inputs are controlled by SEL. During the switchover,
the output will disable LOW for up to three clock cycles of the
previously-selected input clock. The outputs will remain LOW for
up to three clock cycles of the newly-selected clock, after which
the outputs will start from the newly-selected input. A FSEL pin
has been implemented to control the switchover in cases where a
clock source is absent or is driven to DC levels below the minimum
specifications.
The IDT5T93GL161 outputs can be asynchronously
enabled/disabled. When disabled, the outputs will drive to the
value selected by the GL pin. Multiple power and grounds reduce
noise.
IDT5T93GL161
Features
Guaranteed low skew: <75ps (maximum)
Very low duty cycle distortion: <100ps (maximum)
High speed propagation delay: <2.2ns (maximum)
Up to 450MHz operation
Selectable inputs
Hot insertable and over-voltage tolerant inputs
3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL
(3.3V), CML or LVDS input interface
Selectable differential inputs to sixteen LVDS outputs
Power-down mode
At power-up, FSEL should be LOW
2.5V V
DD
-40°C to 85°C ambient operating temperature
Available in TQFP package
Applications
Clock distribution
Pin Assignment
FSEL
PD
GND
V
DD
Q13
Q13
Q14
Q14
GND
SEL
Q15
Q15
Q16
Q16
V
DD
V
DD
G1
GND
GND
V
DD
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
V
DD
A1
A1
GND
1
2
3
4
5
6
7
8
9
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
G2
GND
GND
V
DD
Q12
Q12
Q11
Q11
Q10
Q10
Q9
Q9
V
DD
A2
A2
GND
IDT5T93GL161
64-Lead TQFP E-Pad
10mm x 10mm x 1.0mm package body
Y package
Top View
10
11
12
13
14
15
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GL
GND
V
DD
V
DD
Q5
Q5
Q6
Q6
Q7
Q7
Q8
V
DD
GND
Q8
nc
nc
IDT™ LVDS GLITCHLESS CLOCK BUFFER TERABUFFER™ II
1
IDT5T93GL161 REV. A SEPTEMBER 12, 2008

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