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NB3L202KMNG

Description
1:2 HCSL FANOUT BUFFER
Categorylogic    logic   
File Size148KB,14 Pages
ManufacturerON Semiconductor
Websitehttp://www.onsemi.cn
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NB3L202KMNG Overview

1:2 HCSL FANOUT BUFFER

NB3L202KMNG Parametric

Parameter NameAttribute value
Brand NameON Semiconductor
Is it lead-free?Lead free
MakerON Semiconductor
package instructionHVQCCN,
Manufacturer packaging code485FM
Reach Compliance Codecompliant
Factory Lead Time5 weeks
Samacsys Description2.5V, 3.3V Differential 1:2 HCSL Fanout Buffer 2.5V, 3.3V Differential 1:2 HCSL Fanout Buffer
Other featuresALSO OPERATES AT 2.97 TO 3.63 V SUPPLY
seriesNB3
Input adjustmentDIFFERENTIAL
JESD-30 codeS-XQCC-N16
JESD-609 codee3
length3 mm
Logic integrated circuit typeLOW SKEW CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times4
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeHVQCCN
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
propagation delay (tpd)1.4 ns
Same Edge Skew-Max(tskwd)0.02 ns
Maximum seat height1 mm
Maximum supply voltage (Vsup)2.625 V
Minimum supply voltage (Vsup)2.375 V
Nominal supply voltage (Vsup)2.5 V
surface mountYES
Temperature levelINDUSTRIAL
Terminal surfaceTin (Sn)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width3 mm
minfmax350 MHz
Base Number Matches1
NB3L202K
2.5 V, 3.3 V Differential 1:2
HCSL Fanout Buffer
Description
The NB3L202K is a differential 1:2 Clock fanout buffer
with
High−speed Current Steering Logic (HCSL) outputs. Inputs can
directly accept differential LVPECL, LVDS, and HCSL signals.
Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are
accepted with a proper external Vth reference supply per Figures 4
and 6. The input signal will be translated to HCSL and provides two
identical copies operating up to 350 MHz.
The NB3L202K is optimized for ultra−low phase noise, propagation
delay variation and low output–to–output skew, and is DB200H
compliant. As such, system designers can take advantage of the
NB3L202K’s performance to distribute low skew clocks across the
backplane or the motherboard making it ideal for Clock and Data
distribution applications such as PCI Express, FBDIMM, Networking,
Mobile Computing, Gigabit Ethernet, etc.
Output drive current is set by connecting a 475
W
resistor from
IREF (Pin 10) to GND per Figure 11. Outputs can also interface to
LVDS receivers when terminated per Figure 12.
Features
www.onsemi.com
MARKING
DIAGRAM
QFN16
3x3
CASE 485FM
1
NB3L
202K
ALYWG
G
1
NB3L202K = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
Maximum Input Clock Frequency > 350 MHz
2.5 V
±5%
/ 3.3 V
±10%
Supply Voltage Operation
2 HCSL Outputs
DB200H Compliant
PCIe Gen 3, Gen 4 Compliant
Individual OE Control Pin for Each Output
100 ps Max Output−to−Output Skew Performance
1 ns Typical Propagation Delay
500 ps Typical Rise and Fall Times
80 fs Maximum Additive RMS Phase Jitter
−40°C to +85°C Ambient Operating Temperature
QFN 16−pin Package, 3 mm x 3 mm
These Devices are Pb−Free and are RoHS Compliant
ORDERING INFORMATION
See detailed ordering and shipping information page 13 of this
data sheet.
Typical Applications
PCI Express
FBDIMM
Mobile Computing
Networking
Gigabit Ethernet
©
Semiconductor Components Industries, LLC, 2016
1
January, 2018 − Rev. 4
Publication Order Number:
NB3L202K/D

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