NB3L202K
2.5 V, 3.3 V Differential 1:2
HCSL Fanout Buffer
Description
The NB3L202K is a differential 1:2 Clock fanout buffer
with
High−speed Current Steering Logic (HCSL) outputs. Inputs can
directly accept differential LVPECL, LVDS, and HCSL signals.
Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are
accepted with a proper external Vth reference supply per Figures 4
and 6. The input signal will be translated to HCSL and provides two
identical copies operating up to 350 MHz.
The NB3L202K is optimized for ultra−low phase noise, propagation
delay variation and low output–to–output skew, and is DB200H
compliant. As such, system designers can take advantage of the
NB3L202K’s performance to distribute low skew clocks across the
backplane or the motherboard making it ideal for Clock and Data
distribution applications such as PCI Express, FBDIMM, Networking,
Mobile Computing, Gigabit Ethernet, etc.
Output drive current is set by connecting a 475
W
resistor from
IREF (Pin 10) to GND per Figure 11. Outputs can also interface to
LVDS receivers when terminated per Figure 12.
Features
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MARKING
DIAGRAM
QFN16
3x3
CASE 485FM
1
NB3L
202K
ALYWG
G
1
NB3L202K = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Maximum Input Clock Frequency > 350 MHz
2.5 V
±5%
/ 3.3 V
±10%
Supply Voltage Operation
2 HCSL Outputs
DB200H Compliant
PCIe Gen 3, Gen 4 Compliant
Individual OE Control Pin for Each Output
100 ps Max Output−to−Output Skew Performance
1 ns Typical Propagation Delay
500 ps Typical Rise and Fall Times
80 fs Maximum Additive RMS Phase Jitter
−40°C to +85°C Ambient Operating Temperature
QFN 16−pin Package, 3 mm x 3 mm
These Devices are Pb−Free and are RoHS Compliant
ORDERING INFORMATION
See detailed ordering and shipping information page 13 of this
data sheet.
Typical Applications
PCI Express
FBDIMM
Mobile Computing
Networking
Gigabit Ethernet
©
Semiconductor Components Industries, LLC, 2016
1
January, 2018 − Rev. 4
Publication Order Number:
NB3L202K/D
NB3L202K
Figure 1. Simplified Block Diagram
Figure 2. 16−Pin QFN Pinout
(Top View)
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2
NB3L202K
Table 1. PIN DESCRIPTION
Pin Number
1
2
3
4
5
6
7
8
9
10
Pin Name
GND
CLK_IN
CLK_IN#
VDD
GND_O
DIF_1#
DIF_1
VDD_O
GND
IREF
I/O
Power
I, DIF
I, DIF
Power
Power
O, DIF
O, DIF
Power
Power
I
Ground
Differential True input
Differential Complementary input
Core power supply
Ground for outputs
0.7 V Differential Complementary Output
0.7 V Differential True Output
Power supply for outputs
Ground
A precision resistor is attached to this pin to set the differential output current.
Use R
REF
= 475
W,
1% for 100
W
trace, with 50
W
termination.
Use R
REF
= 412
W,
1% for 85
W
trace, with 43
W
termination.
LVTTL / LVCMOS active low input for enabling output DIF_0/0#. 0 enables outputs,
1 disables outputs. Internal pull down.
LVTTL / LVCMOS active low input for enabling output DIF_1/1#. 0 enables outputs,
1 disables outputs. Internal pull down.
Power supply for outputs
0.7 V Differential True Output
0.7 V Differential Complementary Output
Ground for outputs
The Exposed Pad (EP) on the QFN16 package bottom is thermally connected to the die
for improved heat transfer out of package. The exposed pad must be attached to a
heat−sinking conduit. The pad is electrically connected to the die, and must be electri-
cally and thermally connected to GND on the PC board.
Description
11
12
13
14
15
16
EP
OE0#
OE1#
VDD_O
DIF_0
DIF_0#
GND_O
Exposed
Pad
I, SE
I, SE
Power
O, DIF
O, DIF
Power
Thermal
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NB3L202K
Table 2. ATTRIBUTES
Characteristics
ESD Protection
RPD − Pull−down Resistor
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Oxygen Index: 28 to 34
Human Body Model
Value
> 2000 V
50 kW
Level 1
UL 94 V−0 @ 0.125 in
1344
Table 3. ABSOLUTE MAXIMUM RATINGS
Symbol
V
DD
V
DD_O
V
IH
V
IL
I
OUT
T
A
T
stg
q
JA
q
JC
T
sol
Core Supply Voltage
I/O Supply Voltage
Input High Voltage (Note 2)
Input Low Voltage
Maximum Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 3)
Thermal Resistance (Junction−to−Case) (Note 3)
Wave Solder
0 lfpm
500 lfpm
42
35
4
265
Parameter
Min
−
−
−
−0.5
−
Max
4.6
4.6
4.6
−
24
−40 to +85
−65 to +150
Unit
V
V
V
V
mA
°C
°C
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. Maximum V
IH
is not to exceed maximum V
DD
.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NB3L202K
Table 4. DC CHARACTERISTICS
V
DD
= V
DD_O
= 3.3 V
±10%
or 2.5 V
±5%,
T
A
= −40°C to 85°C
Symbol
POWER SUPPLY CURRENT
V
DD
V
DD_O
Core Power Supply Voltage
Output Power Supply Voltage
V
DD
= 3.3 V
±10%
V
DD
= 2.5 V
±5%
V
DD_O
= 3.3 V
±10%
V
DD_O
= 2.5 V
±5%
2.970
2.375
2.970
2.375
3.3
2.5
3.3
2.5
80
50
15
65
3.630
2.625
3.630
2.625
110
65
23
88
V
V
mA
mA
mA
mA
Characteristics
Min
Typ
Max
Unit
I
DD
+ I
DD_O
Total Power Supply Current (all outputs active @ 350 MHz, R
REF
= 412
W,
R
L
= 43
W)
I
stdby
l
incr
Standby Current, all OE pins de−asserted with inputs @ 350 MHz
Incremental output current for additional output; One OE Enabled
I
stdby
+ l
incr
Standby Current plus incremental current for one additional differential output;
One OE Enabled @ 350 MHz
HCSL OUTPUTS
(Notes 4, 5)
V
OH
V
OL
V
OUT
Output HIGH Voltage
Output LOW Voltage
Output Swing (Single−Ended)
Output Swing (Differential)
660
−150
400
800
850
mV
mV
750
1500
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED
(Note 6) (Figures 4 and 6)
V
IH
V
IL
V
th
V
ISE
CLK_IN/CLK_IN# Single-ended Input HIGH Voltage
CLK_IN/CLK_IN# Single-ended Input LOW Voltage
Input Threshold Reference Voltage Range (Note 7)
Single-ended Input Voltage (V
IH
− V
IL
)
0.5
GND
0.25
0.5
V
DD
V
IH
− 0.3
V
DD
− 1.0
V
DD
V
V
V
V
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Note 8) (Figures 5 and 7)
V
IHD
V
ILD
V
ID
V
IHCMR
I
IL
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
− V
ILD
)
Input Common Mode Range (Differential Configuration) (Note 9) (Figure 8)
Input Leakage Current 0 < V
IN
< V
DD
(Note 10)
0.5
0
0.25
0.5
−5
V
DD
− 0.85
V
IHD
−
0.25
1.3
V
DD
− 0.85
5
V
V
V
V
mA
LVTTL / LVCMOS INPUTS (OEx#)
V
IH
V
IL
I
IL
I
IH
Input HIGH Voltage
Input LOW Voltage
Input LOW Current (V
IN
= GND)
Input HIGH Current (V
IN
= V
DD
)
2.0
−0.3
−10
V
DD
+ 0.3
0.8
+10
100
V
V
mA
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Test configuration is R
S
= 33.2
W,
R
L
= 49.9, C
L
= 2 pF, R
REF
= 475
W.
5. Measurement taken from Single−Ended waveform unless specified otherwise.
6. V
IH
, V
IL,
V
th
and V
ISE
parameters must be complied with simultaneously.
7. V
th
is applied to the complementary input when operating in single−ended mode.
8. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
9. The common mode voltage is defined as V
IH
.
10. Does not include inputs with pulldown resistors.
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