28C16AT-25/P datasheet, PDF - EEWORLD Datasheet

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28C16AT-25/P: Description16K (2K x 8) CMOS EEPROM; File Size123KB，10 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com

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28C16AT-25/P Overview

16K (2K x 8) CMOS EEPROM

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Obsolete Device

28C16A

16K (2K x 8) CMOS EEPROM

FEATURES

• Fast Read Access Time—150 ns

• CMOS Technology for Low Power Dissipation

- 30 mA Active

- 100

µA

Standby

• Fast Byte Write Time—200

µs

or 1 ms

• Data Retention >200 years

• High Endurance - Minimum 10

Erase/Write Cycles

• Automatic Write Operation

- Internal Control Timer

- Auto-Clear Before Write Operation

- On-Chip Address and Data Latches

• Data polling

• Chip Clear Operation

• Enhanced Data Protection

- V

Detector

- Pulse Filter

- Write Inhibit

• Electronic Signature for Device Identification

• 5-Volt-Only Operation

• Organized 2Kx8 JEDEC Standard Pinout

• 24-pin Dual-In-Line Package

• 32-pin PLCC Package

• Available for Extended Temperature Ranges:

- Commercial: 0°C to +70°C

- Industrial: -40°C to +85°C

PACKAGE TYPES

Vcc

• Pin 1 indicator on PLCC on top of package

BLOCK DIAGRAM

I/O0

I/O7

Data Protection

Circuitry

Chip Enable/

Output Enable

Control Logic

Auto Erase/Write

Timing

Data

Poll

Program Voltage

Generation

DESCRIPTION

The Microchip Technology Inc. 28C16A is a CMOS 16K

non-volatile electrically Erasable PROM. The 28C16A

is accessed like a static RAM for the read or write

cycles without the need of external components. Dur-

ing a “byte write”, the address and data are latched

internally, freeing the microprocessor address and data

bus for other operations. Following the initiation of

write cycle, the device will go to a busy state and auto-

matically clear and write the latched data using an

internal control timer. To determine when a write cycle

is complete, the 28C16A uses Data polling. Data poll-

ing allows the user to read the location last written to

when the write operation is complete. CMOS design

and processing enables this part to be used in systems

where reduced power consumption and reliability are

required. A complete family of packages is offered to

provide the utmost flexibility in applications.

A10

Decoder



2004 Microchip Technology Inc.

I/O1

I/O2

Vss

I/O3

I/O4

I/O5

I/O0

I/O1

I/O2

•1

Vcc

A10

I/O7 A0

I/O6 NC

I/O5 I/O0

I/O4

I/O3

A10

I/O7

I/O6

PLCC

Input/Output

Buffers

16K bit

Cell Matrix

DS11125J-page 1

DIP

Y Gating

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