DS1267B
Dual Digital Potentiometer
FEATURES
Two digitally controlled, 256-position
potentiometers
Serial port provides means for setting and
reading both potentiometers
Resistors can be connected in series to
provide increased total resistance
16-pin SO and 20-pin TSSOP packages
Resistive elements are temperature
compensated to ±0.3 LSB relative linearity
Standard resistance values:
– DS1267B-10 ~ 10kΩ
– DS1267B-50 ~ 50kΩ
– DS1267B-100 ~ 100kΩ
Operating Temperature Range:
– Industrial: -40°C to +85°C
PIN ASSIGNMENT
VB
NC
H1
L1
W1
RST
CLK
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
NC
S
OUT
W0
H0
L0
C
OUT
DQ
16-Pin SO (300-mil)
See Mech. Drawings Section
PIN DESCRIPTIONS
L0, L1
H0, H1
W0, W1
V
B
S
OUT
RST
DQ
CLK
C
OUT
V
CC
GND
NC
-
-
-
-
-
-
-
-
-
-
-
-
Low End of Resistor
High End of Resistor
Wiper Terminal of Resistor
Substrate Bias Voltage
Stacked Configuration Output
Serial Port Reset Input
Serial Port Data Input
Serial Port Clock Input
Cascade Port Output
+5V Supply
Ground
No Internal Connection
VB
NC
H1
L1
W1
RST
CLK
NC
NC
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
NC
NC
S
OUT
W0
H0
L0
C
OUT
NC
DQ
20-Pin TSSOP (173-mil)
PART NO.
DS1267BE-010+
DS1267BE-050+
DS1267BE-100+
DS1267BS-010+
DS1267BS-050+
DS1267BS-100+
PIN-
PACKAGE
20 TSSOP
20 TSSOP
20 TSSOP
16 SO
16 SO
16 SO
END-TO-END
RESISTANCE (kΩ)
10
50
100
10
50
100
19-6589; Rev 1; 1/14
Maxim Integrated
1
DS1267B
DESCRIPTION
The DS1267B Dual Digital Potentiometer Chip consists of two digitally controlled, solid-state
potentiometers. Each potentiometer is composed of 256 resistive sections. Between each resistive section
and both ends of the potentiometer are tap points which are accessible to the wiper. The position of the
wiper on the resistive array is set by an 8-bit value that controls which tap point is connected to the wiper
output. Communication and control of the device are accomplished via a 3-wire serial port interface. This
interface allows the device wiper position to be read or written.
Both potentiometers can be connected in series (or stacked) for an increased total resistance with the
same resolution. For multiple-device, single-processor environments, the DS1267B can be cascaded or
daisy-chained. This feature provides for control of multiple devices over a single 3-wire bus.
The DS1267B is offered in three standard resistance values which include 10kΩ, 50kΩ, and 100kΩ
versions. Available packages for the device include a 16-pin SO and 20-pin TSSOP.
OPERATION
The DS1267B contains two 256-position potentiometers whose wiper positions are set by an 8-bit value.
These two 8-bit values are written to a 17-bit I/O shift register that is used to store the two wiper positions
and the stack select bit when the device is powered. A block diagram of the DS1267B is presented in
Figure 1.
Communication and control of the DS1267B are accomplished through a 3-wire serial port interface that
drives an internal control logic unit. The 3-wire serial interface consists of the three input signals:
RST
,
CLK, and DQ.
The
RST
control signal is used to enable the 3-wire serial port operation of the device. The chip is
selected when
RST
is high;
RST
must be high to begin any communication to the DS1267B. The CLK
signal input is used to provide timing synchronization for data input and output. The DQ signal line is
used to transmit potentiometer wiper settings and the stack select bit configuration to the 17-bit I/O shift
register of the DS1267B.
Figure 9(a) presents the 3-wire serial port protocol. As shown, the 3-wire port is inactive when the
RST
signal input is low. Communication with the DS1267B requires the transition of the
RST
input from a
low state to a high state. Once the 3-wire port has been activated, data is entered into the part on the low
to high transition of the CLK signal inputs. Three-wire serial timing requirements are provided in the
timing diagrams of Figure 9(b)-(c).
Data written to the DS1267B over the 3-wire serial interface is stored in the 17-bit I/O shift register (see
Figure 2). The 17-bit I/O shift register contains both 8-bit potentiometer wiper position values and the
stack select bit. The composition of the I/O shift register is presented in Figure 2. Bit 0 of the I/O shift
register contains the stack select bit, which will be discussed in the section entitled
Stacked
Configuration.
Bits 1 through 8 of the I/O shift register contain the potentiometer-1 wiper position value.
Bit 1 contains the MSB of the wiper setting for potentiometer-1 and bit 8 the LSB for the wiper setting.
Bits 9 through 16 of the I/O shift register contain the value of the potentiometer-0 wiper position, with the
MSB for the wiper position occupying bit 9 and the LSB bit 16.
DS1267B
DS1267B BLOCK DIAGRAM
Figure 1
I/O SHIFT REGISTER
Figure 2
Transmission of data always begins with the stack select bit followed by the potentiometer-1 wiper
position value and lastly the potentiometer-0 wiper position value.
When wiper position data is to be written to the DS1267B, 17 bits (or some integer multiple) of data
should always be transmitted. Transactions which do not send a complete 17 bits (or multiple) will leave
the register incomplete and possibly an error in the desired wiper positions.
After a communication transaction has been completed, the
RST
signal input should be taken to a low
state to prevent any inadvertent changes to the device shift register. Once
RST
has reached a low state,
the contents of the I/O shift register are loaded into the respective multiplexers for setting wiper position.
A new wiper position will only engage after a
RST
transition to the inactive state. On device power-up
the DS1267B wiper positions will be set at 50% of the total resistance or binary value 1000 0000.
Maxim Integrated .............................................................................................................................................................................................
3
DS1267B
STACKED CONFIGURATION
The potentiometers of the DS1267B can be connected in series as shown in Figure 3. This is referred to
as the stacked configuration. The stacked configuration allows the user to double the total end-to-end
resistance of the part and the number of steps to 512 (or 9 bits of resolution).
The wiper output for the combined stacked potentiometer will be taken at the S
OUT
pin, which is the
multiplexed output of the wiper of potentiometer-0 (W0) or potentiometer-1 (W1). The potentiometer
wiper selected at the S
OUT
output is governed by the setting of the stack select bit (bit 0) of the 17-bit I/O
shift register. If the stack select bit has value 0, the multiplexed output, S
OUT
, will be that of the
potentiometer-0 wiper. If the stack select bit has value 1, the multiplexed output, S
OUT
, will be that of the
potentiometer-1 wiper.
STACKED CONFIGURATION
Figure 3
CASCADE OPERATION
A feature of the DS1267B is the ability to control multiple devices from a single processor. Multiple
DS1267Bs can be linked or daisy-chained as shown in Figure 4. As a data bit is entered into the I/O shift
register of the DS1267B a bit will appear at the C
OUT
output within a maximum delay of 50 nanoseconds.
The stack select bit of the DS1267B will always be the first out the part at the beginning of a transaction.
Additionally the C
OUT
pin is always active regardless of the state of
RST
. This allows one to read the I/O
shift register without changing its value.
CASCADING MULTIPLE DEVICES
Figure 4
Maxim Integrated .............................................................................................................................................................................................
4
DS1267B
The C
OUT
output of the DS1267B can be used to drive the DQ input of another DS1267B. When
connecting multiple devices, the total number of bits transmitted is always 17 times the number of
DS1267Bs in the daisy chain.
An optional feedback resistor can be placed between the C
OUT
terminal of the last device and the first
DS1267B DQ input, thus allowing the controlling processor to read as well as write data or circularly
clock data through the daisy chain. The value of the feedback or isolation resistor should be in the range
from 2Ω to 10kΩ.
When reading data via the C
OUT
pin and isolation resistor, the DQ line is left floating by the reading
device. When
RST
is driven high, bit 17 is present on the C
OUT
pin, which is fed back to the input DQ
pin through the isolation resistor. When the CLK input transitions low to high, bit 17 is loaded into the
first position of the I/O shift register and bit 16 becomes present on C
OUT
and DQ of the next device. After
17 bits (or 17 times the number of DS1267Bs in the daisy chain), the data has shifted completely around
and back to its original position. When
RST
transitions to the low state to end data transfer, the value (the
same as before the read occurred) is loaded into the wiper-0, wiper-1, and stack select bit I/O register.
ABSOLUTE AND RELATIVE LINEARITY
Absolute linearity, also known as integral nonlinearity, is defined as the difference between the actual
measured output voltage and the expected output voltage. Figure 5 presents the test circuit used to
measure absolute linearity. Absolute linearity is given in terms of a minimum increment or expected
output when the wiper is moved one position. In the case of the test circuit, a minimum increment (MI) or
one LSB would equal 10/512 volts. The equation for absolute linearity is given as follows:
(1)
ABSOLUTE LINEARITY (INL)
AL={V
O
(actual) - V
O
(expected)}/MI
Relative Linearity, also known as differential nonlinearity, is a measure of error between two adjacent
wiper position points and is given in terms of MI by equation (2).
(2)
RELATIVE LINEARITY (DNL)
RL={V
O
(n+1) - V
O
(n)}/MI
Figure 6 is a plot of absolute linearity and relative linearity versus wiper position for the DS1267B at
25°C. The specification for absolute linearity of the DS1267B is ±0.75 MI typical. The specification for
relative linearity of the DS1267B is ±0.3 MI typical.
Maxim Integrated .............................................................................................................................................................................................
5
京公网安备 11010802033920号
EEWORLD
