AT17F040A and AT17F080A
FPGA Configuration Flash Memory
DATASHEET
Features
Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed
to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs)
3.3V Output Capability
5.0V Tolerant I/O Pins
Program Support using the Atmel ATDH2200E System, ATDH2225 ISP cable,
or Third-party Programmers
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT40K and AT94K Devices, Altera
®
FLEX
®
, Excalibur
™
,
Stratix
®
, Cyclone
™
, and APEX
™
Devices
Cascadable Read-back to Support Additional Configurations or Higher-density
Arrays
Low-power CMOS FLASH Process
Available in 8-pad LAP and 20-lead PLCC Packages
Emulation of the Atmel AT24C Serial EEPROMs
Low-power Standby Mode
Single Device Capable of Holding 4-Bitstream Files Allowing Simple System
Reconfiguration
Fast Serial Download Speeds up to 33MHz
Endurance: 100,000 Write Cycles Typical
Green (Lead/Halide-free/ROHS compliant) Package Options
Description
The Atmel
®
AT17FxxxA Series of In-System Programmable Configuration
PROMs (Configurators) provide an easy-to-use, cost-effective configuration
memory solution for FPGAs. The AT17FxxxA Series devices are packaged in the
8-pad LAP and 20-lead PLCC (Table
1-1).
The AT17FxxxA Series Configurators
use a simple serial-access procedure to configure one or more FPGA devices.
The AT17FxxxA Series Configurators can be programmed with industry-standard
programmers, the Atmel ATDH2200E Programming Kit or the Atmel ATDH2225
ISP Cable.
Table 1.
Package
8-pad LAP
20-lead PLCC
AT17FxxxA Series Packages
AT17F040A
Yes
Yes
AT17F080A
Yes
Yes
Atmel-2823E-CNFG-AT17F040A-080A-Datasheet_012015
1.
Pin Configurations
Table 1-1.
Pin
DATA
(1)
DCLK
(1)
Pin Descriptions
Description
Three-state DATA output for FPGA Configuration.
Open-collector bi-directional pin for
configuration programming.
Three-state Clock.
Functions as an input when the Configurator is in programming mode (i.e.
SER_EN is Low) and as an output during FPGA configuration.
Enable Page Download Mode Input.
When PAGE_EN is high the configuration download address
space is partitioned into four equal pages. This gives users the ability to easily store and retrieve
multiple configuration bitstreams from a single configuration device. This input works in conjunction
with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired. When SER_EN is
Low (ISP mode) this pin has no effect.
(2)
PAGE_EN
(2)
PAGESEL[1:0]
Page Select Inputs.
Used to determine which of the four memory pages are targeted during a serial
configuration download. The address space for each of the pages is shown in
Table 1-2.
When
SER_EN is Low (ISP mode) these pins have no effect.
Output Enable (Active High) and RESET (Active Low) when SER_EN is High.
A Low level on
RESET/OE resets both the address and bit counters. A High level (with nCS Low) enables the data
output driver.
Chip Enable Input (Active Low).
A Low level (with OE High) allows DCLK to increment the address
counter and enables the data output driver. A High level on nCS disables both the address and bit
counters and forces the device into a low-power standby mode. Note that this pin will
not
enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low).
Ground.
A 0.2μF decoupling capacitor between V
CC
and GND is recommended.
Cascade Select Output (when SER_EN is High).
This output goes Low when the internal address
counter has reached its maximum value. If the PAGE_EN input is set High, the maximum value is the
highest address in the selected partition. The PAGESEL[1:0] inputs are used to make the four
partition selections. If the PAGE_EN input is set Low, the device is not partitioned and the address
maximum value is the highest address in the device (Table
1-2).
In a daisy chain of the AT17FxxxA
Series devices, the nCASC pin of one device must be connected to the nCS input of the next device
in the chain. It will stay Low as long as nCS is Low and OE is High. It will then follow nCS until OE
goes Low; thereafter, nCASC will stay High until the entire EEPROM is read again.
Device Selection Input, (when SER_EN Low).
The input is used to enable (or chip select) the
device during programming (i.e., when SER_EN is Low). Refer to the Atmel AT17FxxxA
Programming Specification available at
www.atmel.com
for additional details.
Open Collector Reset State Indicator.
Driven Low during power-up reset, released when power-up
is complete. (recommended 4.7k pull-up on this pin if used).
RESET/OE
(1)
nCS
(1)
GND
nCASC
A2
(1)
READY
SER_EN
V
CC
Notes:
(1)
Serial Enable Input.
Must remain High during FPGA configuration operations. Bringing SER_EN
Low enables the 2-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be
tied to V
CC
.
Device Power Supply.
+3.3V (±10%)
1.
2.
Internal 20K pull-up resistor
Internal 30K pull-up resistor
2
AT17F040A/080A [DATASHEET]
Atmel-2823E-CNFG-AT17F040A-080A-Datasheet_012015
Table 1-2.
Address Space (PAGESEL[1:0])
AT17F040A (4Mb)
00000 – 0FFFFh
10000 – 1FFFFh
20000 – 2FFFFh
30000 – 3FFFFh
00000 – 3FFFFh
AT17F080A (8Mb)
00000 – 1FFFFh
20000 – 3FFFFh
40000 – 5FFFFh
60000 – 7FFFFh
00000 – 7FFFFh
Paging Decodes
PAGESEL = 00, PAGE_EN = 1
PAGESEL = 01, PAGE_EN = 1
PAGESEL = 10, PAGE_EN = 1
PAGESEL = 11, PAGE_EN = 1
PAGESEL = XX, PAGE_EN = 0
Table 1-3.
Name
DATA
DCLK
PAGE_EN
PAGESEL0
PAGESEL1
RESET/
OE
nCS
GND
nCASC
A2
READY
SER_EN
V
CC
Figure 1-1.
Pin Configurations
I/O
I/O
I
I
I
I
I
I
–
O
I
O
I
–
8-pad LAP
1
2
—
—
—
3
4
5
6
20-lead PLCC
2
4
16
11
7
8
9
10
12
6
—
7
8
12
15
18
20
Pinouts
8-pad LAP
(Top View)
20-lead PLCC
(Top View)
V
CC
20
NC
DCLK
RESET/OE
nCS
2
3
4
7
6
5
SER_EN
(A2) nCASC
GND
DCLK
NC
NC
PAGESEL1
RESET/OE
4
5
6
7
8
NC
1
19
3
2
NC
DATA
1
8
V
CC
DATA
18
17
16
15
14
10
12
13
11
9
SER_EN
NC
PAGE_EN
READY
NC
nCS
(A2) nCASC
PAGESEL0
GND
Note:
Drawings are not to scale.
NC
AT17F040A/080A [DATASHEET]
Atmel-2823E-CNFG-AT17F040A-080A-Datasheet_012015
3
2.
Block Diagram
Figure 2-1.
Block Diagram
READY
Power-on
Reset
Reset
Clock/Oscillator
Logic
DCLK
PAGE_EN
PAGESEL0
PAGESEL1
Configuration
Page Select
nCASC(A2)
Serial Download Logic
2-wire Serial Programming
DATA
Flash
Memory
CE/WE/OE
Data
Address
nCS
Control Logic
RESET/OE
SER_EN
4
AT17F040A/080A [DATASHEET]
Atmel-2823E-CNFG-AT17F040A-080A-Datasheet_012015
3.
Device Description
The control signals for the configuration memory device (nCS, RESET/OE and DCLK) interface directly with the
FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data
from the configuration device without requiring an external intelligent controller.
The RESET/OE and nCS pins control the tri-state buffer on the DATA output pin and enable the address
counter. When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its
DATA pin. The nCS pin also controls the output of the AT17FxxxA Series Configurator. If nCS is held High after
the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is
subsequently driven High, the counter and the DATA output pin are enabled. When RESET/OE is driven Low
again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of nCS.
When the configurator has driven out all of its data and nCASC is driven Low, the device tri-states the DATA pin
to avoid contention with other configurators. Upon power-up, the address counter is automatically reset.
4.
FPGA Master Serial Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The
program is loaded either automatically upon power-up or on command, depending on the state of the FPGA
mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory.
The AT17FxxxA Serial Configuration PROM has been designed for compatibility with the Master Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Altera applications.
5.
Control of Configuration
Most connections between the FPGA device and the AT17FxxxA Serial Configurator PROM are simple and
self-explanatory.
The DATA output of the AT17FxxxA Series Configurator drives DIN of the FPGA devices.
The DCLK output of the AT17FxxxA drives the DCLK input data of the FPGA.
The nCASC output of a AT17FxxxA Series Configurator drives the nCS input of the next Configurator in a
cascade chain of configurator devices.
SER_EN must be at logic High level (internal pull-up resistor provided) except during ISP.
The READY pin is available as an open-collector indicator of the device’s reset status; it is driven Low
while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete.
PAGE_EN must REMAIN Low if download paging is not desired. If paging is desired, PAGE_EN must be
High and the PAGESEL pins must be set to High or Low such that the desired page is selected
(Table
1-2).
6.
Cascading Serial Configuration Devices
For multiple FPGAs configured as a daisy-chain or for FPGAs requiring larger configuration memories,
cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator asserts its nCASC output
Low and disables its DATA line driver. The second configurator recognizes the Low level on its nCS input and
enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE
on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive
(High) level.
AT17F040A/080A [DATASHEET]
Atmel-2823E-CNFG-AT17F040A-080A-Datasheet_012015
5
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