AT17F040A-30JU datasheet, PDF - EEWORLD Datasheet

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AT17F040A-30JU: DescriptionFPGA - Configuration Memory SER CONFIG FLASH-4M ALTERA PINOUT-30MHZ; Categorystorage storage; File Size434KB，14 Pages; ManufacturerMicrochip; Websitehttps://www.microchip.com; Environmental Compliance

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AT17F040A-30JU Overview

FPGA - Configuration Memory SER CONFIG FLASH-4M ALTERA PINOUT-30MHZ

AT17F040A-30JU Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Microchip
package instruction	LEAD AND HALIDE FREE, PLASTIC, MS-018AA, LCC-20
Reach Compliance Code	compliant
Factory Lead Time	5 weeks
Maximum clock frequency (fCLK)	10 MHz
JESD-30 code	S-PQCC-J20
JESD-609 code	e3
length	8.9662 mm
memory density	4194304 bit
Memory IC Type	CONFIGURATION MEMORY
memory width	1
Humidity sensitivity level	2
Number of functions	1
Number of terminals	20
word count	4194304 words
character code	4000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	4MX1
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Parallel/Serial	SERIAL
Peak Reflow Temperature (Celsius)	245
Certification status	Not Qualified
Maximum seat height	4.572 mm
Maximum supply voltage (Vsup)	3.63 V
Minimum supply voltage (Vsup)	2.97 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Matte Tin (Sn) - annealed
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	40
width	8.9662 mm
Maximum write cycle time (tWC)	0.03 ms
Base Number Matches	1

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AT17F040A and AT17F080A

FPGA Configuration Flash Memory

DATASHEET

Features



Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed

to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs)

3.3V Output Capability

5.0V Tolerant I/O Pins

Program Support using the Atmel ATDH2200E System, ATDH2225 ISP cable,

or Third-party Programmers

In-System Programmable (ISP) via 2-wire Bus

Simple Interface to SRAM FPGAs

Compatible with Atmel AT40K and AT94K Devices, Altera

FLEX

, Excalibur

™

Stratix

, Cyclone

™

, and APEX

™

Devices

Cascadable Read-back to Support Additional Configurations or Higher-density

Arrays

Low-power CMOS FLASH Process

Available in 8-pad LAP and 20-lead PLCC Packages

Emulation of the Atmel AT24C Serial EEPROMs

Low-power Standby Mode

Single Device Capable of Holding 4-Bitstream Files Allowing Simple System

Reconfiguration

Fast Serial Download Speeds up to 33MHz

Endurance: 100,000 Write Cycles Typical

Green (Lead/Halide-free/ROHS compliant) Package Options

Description

The Atmel

AT17FxxxA Series of In-System Programmable Configuration

PROMs (Configurators) provide an easy-to-use, cost-effective configuration

memory solution for FPGAs. The AT17FxxxA Series devices are packaged in the

8-pad LAP and 20-lead PLCC (Table

1-1).

The AT17FxxxA Series Configurators

use a simple serial-access procedure to configure one or more FPGA devices.

The AT17FxxxA Series Configurators can be programmed with industry-standard

programmers, the Atmel ATDH2200E Programming Kit or the Atmel ATDH2225

ISP Cable.

Table 1.

Package

8-pad LAP

20-lead PLCC

AT17FxxxA Series Packages

AT17F040A

Yes

AT17F080A

Yes

Atmel-2823E-CNFG-AT17F040A-080A-Datasheet_012015

Device Description

The control signals for the configuration memory device (nCS, RESET/OE and DCLK) interface directly with the

FPGA device control signals. All FPGA devices can control the entire configuration process and retrieve data

from the configuration device without requiring an external intelligent controller.

The RESET/OE and nCS pins control the tri-state buffer on the DATA output pin and enable the address

counter. When RESET/OE is driven Low, the configuration device resets its address counter and tri-states its

DATA pin. The nCS pin also controls the output of the AT17FxxxA Series Configurator. If nCS is held High after

the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-stated. When OE is

subsequently driven High, the counter and the DATA output pin are enabled. When RESET/OE is driven Low

again, the address counter is reset and the DATA output pin is tri-stated, regardless of the state of nCS.

When the configurator has driven out all of its data and nCASC is driven Low, the device tri-states the DATA pin

to avoid contention with other configurators. Upon power-up, the address counter is automatically reset.

FPGA Master Serial Mode Summary

The I/O and logic functions of any SRAM-based FPGA are established by a configuration program. The

program is loaded either automatically upon power-up or on command, depending on the state of the FPGA

mode pins. In Master mode, the FPGA automatically loads the configuration program from an external memory.

The AT17FxxxA Serial Configuration PROM has been designed for compatibility with the Master Serial mode.

This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as well as Altera applications.

Control of Configuration

Most connections between the FPGA device and the AT17FxxxA Serial Configurator PROM are simple and

self-explanatory.



The DATA output of the AT17FxxxA Series Configurator drives DIN of the FPGA devices.

The DCLK output of the AT17FxxxA drives the DCLK input data of the FPGA.

The nCASC output of a AT17FxxxA Series Configurator drives the nCS input of the next Configurator in a

cascade chain of configurator devices.

SER_EN must be at logic High level (internal pull-up resistor provided) except during ISP.

The READY pin is available as an open-collector indicator of the device’s reset status; it is driven Low

while the device is in its power-on reset cycle and released (tri-stated) when the cycle is complete.

PAGE_EN must REMAIN Low if download paging is not desired. If paging is desired, PAGE_EN must be

High and the PAGESEL pins must be set to High or Low such that the desired page is selected

(Table

1-2).

Cascading Serial Configuration Devices

For multiple FPGAs configured as a daisy-chain or for FPGAs requiring larger configuration memories,

cascaded configurators provide additional memory.

After the last bit from the first configurator is read, the clock signal to the configurator asserts its nCASC output

Low and disables its DATA line driver. The second configurator recognizes the Low level on its nCS input and

enables its DATA output.

After configuration is complete, the address counters of all cascaded configurators are reset if the RESET/OE

on each configurator is driven to its active (Low) level.

If the address counters are not to be reset upon completion, then the RESET/OE input can be tied to its inactive

(High) level.

AT17F040A/080A [DATASHEET]

Atmel-2823E-CNFG-AT17F040A-080A-Datasheet_012015

AT17F040A-30JU Related Products

	AT17F040A-30JU	AT17F080A-30JU	AT17F040A-30CU	AT17F040A-30QI	AT17F080A-30QI	AT17F040A-30QC	AT17F080A-30QC	AT17F080A-30CU
Description	FPGA - Configuration Memory SER CONFIG FLASH-4M ALTERA PINOUT-30MHZ	FPGA - Configuration Memory SER CONFIG FLASH-8M ALTERA PINOUT-30MHZ	FPGA - Configuration Memory SER CONFIG FLASH-4M ALTERA PINOUT-30MHZ	IC FLASH CONFIG 4M 32TQFP	IC FLASH CONFIG 8M 32TQFP	IC FLASH CONFIG 4M 32TQFP	IC FLASH CONFIG 8M 32TQFP	IC FLASH CONFIG 8M 8LAP

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