Unbuffered DIMM
DDR3 SDRAM
DDR3 SDRAM Specification
240pin Unbuffered DIMM based on 1Gb D-die
64/72-bit Non-ECC/ECC
82/100FBGA with Lead-Free
(RoHS compliant)
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AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE
CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER-
WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL-
OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT
GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
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* Samsung Electronics reserves the right to change products or specification without notice.
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Table Contents
DDR3 SDRAM
1.0 DDR3 Unbuffered DIMM Ordering Information ...........................................................................................................4
2.0 Key Features .................................................................................................................................................................4
3.0 Address Configuration .................................................................................................................................................4
4.0 x64 DIMM Pin Configurations (Front side/Back side) ................................................................................................5
5.0 x72 DIMM Pin Configurations (Front side/Back side) ................................................................................................6
6.0 Pin Description ..............................................................................................................................................................7
7.0 SPD and Thermal Sensor for ECC UDIMMs ...............................................................................................................7
8.0 Input/Output Functional Description ..........................................................................................................................8
8.1 Address Mirroring Feature ....................................................................................................................................9
8.1.1 DRAM Pin Wiring for Mirroring ...................................................................................................................9
9.0 Functional Block Diagram: ........................................................................................................................................10
9.1 512MB, 64Mx64 Module (Populated as 1 rank of x16 DDR3 SDRAMs) ............................................................10
9.2 1GB, 128Mx64 Module (Populated as 1 rank of x8 DDR3 SDRAMs) ................................................................11
9.3 1GB, 128Mx72 ECC Module (Populated as 1 rank of x8 DDR3 SDRAMs) ........................................................12
9.4 2GB, 256Mx64 Module(Populated as 2 ranks of x8 DDR3 SDRAMs) ...............................................................13
9.5 2GB, 256Mx72 ECC Module(Populated as 2 ranks of x8 DDR3 SDRAMs) .......................................................14
10.0 Absolute Maximum Ratings .....................................................................................................................................15
10.1 Absolute Maximum DC Ratings .........................................................................................................................15
10.2 DRAM Component Operating Temperature Range ..........................................................................................15
11.0 AC & DC Operating Conditions ...............................................................................................................................15
11.1 Recommended DC Operating Conditions (SSTL - 15) .....................................................................................15
12.0 AC & DC Input Measurement Levels .......................................................................................................................16
12.1 AC and DC Logic Input Levels for Single-ended Signals ................................................................................16
12.2 V
REF
Tolerances. .................................................................................................................................................17
12.3 AC and DC Logic Input Levels for Differential Signals ...................................................................................18
12.3.1 Differential Signals Definition ...............................................................................................................................18
12.3.2 Differential Swing Requirement for Clock (CK - CK) and Strobe (DQS - DQS) ................................................18
12.3.3 Single-ended Requirements for Differential Signals ..........................................................................................19
12.3.4 Differential Input Cross Point Voltage .................................................................................................................20
12.4 Slew Rate Definition for Single Ended Input Signals ......................................................................................20
12.5 Slew rate definition for Differential Input Signals ............................................................................................20
13.0 AC and DC Output Measurement Levels .................................................................................................................21
13.1 Single Ended AC and DC Output Levels ...........................................................................................................21
13.2 Differential AC and DC Output Levels ...............................................................................................................21
13.3 Single Ended Output Slew Rate ........................................................................................................................21
13.4 Differential Output Slew Rate ............................................................................................................................22
14.0 IDD specification definition ......................................................................................................................................23
14.1 IDD SPEC Table ...................................................................................................................................................25
15.0 Input/Output Capacitance ........................................................................................................................................28
15.1. Non ECC UDIMM ................................................................................................................................................28
15.2. ECC UDIMM ........................................................................................................................................................28
16.0 Electrical Characteristics and AC timing ................................................................................................................29
16.1 Refresh Parameters by Device Density ............................................................................................................29
16.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin .........................................................29
16.3 Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin ..........................................................29
16.3.1 Speed Bin Table Notes ............................................................................................................................30
17.0 Timing Parameters by Speed Grade .......................................................................................................................31
17.1 Jitter Notes ..........................................................................................................................................................34
17.2 Timing Parameter Notes .....................................................................................................................................35
17.3 Address / Command Setup, Hold and Derating : .............................................................................................36
17.4 Data Setup, Hold and Slew Rate Derating : ......................................................................................................42
18.0 Physical Dimensions : .............................................................................................................................................47
18.1 64Mbx16 based 64Mx64 Module(1 Rank) .........................................................................................................47
18.2 128Mbx8 based 128Mx64/x72 Module(1 Rank) ................................................................................................48
18.3 128Mbx8 based 256Mx64/x72 Module(2 Ranks) ..............................................................................................49
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1.0 DDR3 Unbuffered DIMM Ordering Information
Part Number
M378B6474DZ1-CF8/H9
M378B2873DZ1-CF8/H9
M391B2873DZ1-CF8/H9
M378B5673DZ1-CF8/H9
M391B5673DZ1-CF8/H9
Note :
- "##" - F8/H9
- F8 - 1066Mbps 7-7-7 & H9 - 1333Mbps 9-9-9
DDR3 SDRAM
Density
512MB
1GB
1GB
2GB
2GB
Organization
64Mx64
128Mx64
128Mx72
256Mx64
256Mx72
Component Composition
64Mx16(K4B1G1646D-HC##)*4
128Mx8(K4B1G0846D-HC##)*8
128Mx8(K4B1G0846D-HC##)*9
128Mx8(K4B1G0846D-HC##)*16
128Mx8(K4B1G0846D-HC##)*18
Number of
Rank
1
1
1
2
2
Height
30mm
30mm
30mm
30mm
30mm
2.0 Key Features
Speed
tCK(min)
CAS Latency
tRCD(min)
tRP(min)
tRAS(min)
tRC(min)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DDR3-1066
7-7-7
1.875
7
13.125
13.125
37.5
50.625
DDR3-1333
9-9-9
1.5
9
13.5
13.5
36
49.5
Unit
ns
tCK
ns
ns
ns
ns
JEDEC standard 1.5V ± 0.075V Power Supply
V
DDQ
= 1.5V ± 0.075V
533MHz f
CK
for 1066Mb/sec/pin, 667MHz f
CK
for 1333Mb/sec/pin
8 independent internal bank
Programmable CAS Latency: 6,7,8,9,10
Programmable Additive Latency(Posted CAS) : 0, CL - 2, or CL - 1 clock
Programmable CAS Write Latency(CWL) = 6(DDR3-1066) and 7(DDR3-1333)
8-bit pre-fetch
Burst Length: 8 (Interleave without any limit, sequential with starting address “000” only), 4 with tCCD = 4 which does not allow seamless read or
write [either On the fly using A12 or MRS]
Bi-directional Differential Data Strobe
Internal(self) calibration : Internal self calibration through ZQ pin (RZQ : 240 ohm ± 1%)
On Die Termination using ODT pin
Average Refresh Period 7.8us at lower then T
CASE
85°C, 3.9us at 85°C < T
CASE
≤
95°C
Asynchronous Reset
3.0 Address Configuration
Organization
128x8(1Gb) based Module
64x16(1Gb) based Module
Row Address
A0-A13
A0-A12
Column Address
A0-A9
A0-A9
Bank Address
BA0-BA2
BA0-BA2
Auto Precharge
A10/AP
A10/AP
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