TDA8026
Multiple smart card slot interface IC
Rev. 1.1 — 30 June 2016
Product data sheet
1. General description
The TDA8026 is a cost-effective, analog interface for addressing multiple smart card slots
in a Point Of Sales (POS) terminal. It can address up to two main cards (synchronous or
asynchronous smart cards supported) and up to four Security Access Modules (SAMs).
Its packaging supports the latest payment terminal security requirements.
2. Features and benefits
I
2
C-bus controlled IC card interface in a TFBGA64 package
Supply voltage between 2.7 V and 5.5 V
Dedicated microcontroller interface supply voltage (V
DD(INTF)
)
Shutdown mode ensures very low power consumption when the TDA8026 is inactive
Programmable power reduction modes triggered when the card slots are inactive
V
CC(n)
generation via DC-to-DC converter: two card slots can be fully loaded, the three
others in reduced consumption mode
Two clock input pins: CLKIN1 for card slot 1 and CLKIN2 for card slots 2 to 5
Two transparent I/O lines on microcontroller side, one for card slot 1 and the other for
card slots 2 to 5
Five protected, half-duplex, bidirectional, buffered I/O lines with current limitation at
15 mA and a maximum frequency 1 MHz
Two I
2
C-bus controlled auxiliary I/O lines
V
CC(n)
regulation on all card slots at I
CC
55 mA:
5 V, 3 V or 1.8 V
5 %
Current spikes of 40 nAs up to 20 MHz for 5 V cards with controlled rise and fall
times
Current limitation of approximately 100 mA
Thermal protection and short-circuit protection on all card contacts
Automatic activation and deactivation sequences initiated by the software or hardware
in the event of a short-circuit, card take-off or voltage drop-out for V
DD(INTF)
, V
DD
or V
UP
Enhanced ElectroStatic Discharge (ESD) protection on the card-side up to 6 kV
20 MHz clock input
Card clock generation up to 20 MHz and dividable by 1, 2, 4 or 5 with synchronous
frequency changes:
Stop, HIGH or LOW
Clock frequency between 1 MHz and 2.2 MHz in card low-power mode
Current limitation on pin CLK
(n)
NXP Semiconductors
TDA8026
Multiple smart card slot interface IC
RST
(n)
signal lines with current limitation at 20 mA, controlled by an embedded
programmable clock pulse counter on asynchronous cards or by a register on
synchronous cards
ISO 7816-3 and EMV 4.3
1
payment systems compatibility
V
DD(INTF)
supply voltage supervisor ensures correct communication between
microcontroller and circuit; threshold internally fixed or set using an external resistor
bridge
V
DD
supply voltage supervisor for spike suppression during power-on and emergency
deactivation at power-off; threshold internally fixed
Card presence input with a 17.8 ms (typical) built-in debouncing system on card slots
1 and 2
One interrupt signal (IRQN)
3. Applications
Point Of Sale terminals
Multiple SAM contact readers
4. Quick reference data
Table 1.
Quick reference data
V
DD
= V
DD(INTF)
= 3.3 V; f
clk(ext)
= 10 MHz; GND = 0 V; inductor = 10
H; decoupling capacitors on pins V
DD
and V
UP
= 10
F;
T
amb
= 25
C unless otherwise specified.
Symbol
Supply
V
DD
supply voltage
on pin V
DD
; DC-to-DC converter on
on pin V
DD
; DC-to-DC converter off and
V
CC(n)
pin = 5 V
I
DD
supply current
shutdown mode
Standby mode
clock-stop mode; all card slots in this mode;
f
clk(ext)
stopped on pins CLK
(n)
; pins CLKIN1
and CLKIN2 either stopped, HIGH-level or
LOW-level
active mode; all V
CC(n)
pins = 5 V; f
clk(ext)
on
pins CLK
(n)
= 5 MHz; I
CC(1)
= I
CC(2)
= 55 mA;
I
CC(3)
= I
CC(4)
= I
CC(5)
= 2 mA
V
DD(INTF)
I
DD(INTF)
interface supply voltage on pin V
DD(INTF)
interface supply current shutdown mode
active mode; all V
CC(n)
pins = 5 V; f
clk(ext)
on
pins CLK
(n)
= 5 MHz
[2]
[3]
[1]
[1]
Parameter
Conditions
Min
2.7
5.25
-
-
-
Typ
-
-
25
300
3.7
Max
5.5
5.5
40
450
-
Unit
V
V
A
A
mA
-
210
260
mA
1.6
-
-
-
10
35
3.6
15
-
V
A
A
1.
for C3 version
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
TDA8026_1
Product data sheet
Rev. 1.1 — 30 June 2016
2 of 61
NXP Semiconductors
TDA8026
Multiple smart card slot interface IC
Table 1.
Quick reference data
…continued
V
DD
= V
DD(INTF)
= 3.3 V; f
clk(ext)
= 10 MHz; GND = 0 V; inductor = 10
H; decoupling capacitors on pins V
DD
and V
UP
= 10
F;
T
amb
= 25
C unless otherwise specified.
Symbol
V
CC
Parameter
supply voltage
Conditions
active mode; 2.7 V < V
DD
< 5.5 V
5 V card; DC I
CC(n)
55 mA
3 V card; DC I
CC(n)
55 mA
1.8 V card; DC I
CC(n)
35 mA
active mode; AC current pulses with
I < 200 mA, t < 400 ns and f < 20 MHz
5 V card; current spikes of 40 nAs
3 V card; current spikes of 17.5 nAs
1.8 V card; current spikes of 11.1 nAs
V
ripple(p-p)
I
CC
peak-to-peak ripple
voltage
supply current
20 kHz to 200 MHz with default Register6
(Slew Rate register) settings
V
CC(n)
= 5 V
V
CC
(n) = 3 V
V
CC
(n) = 1.8 V
sum of all card supply currents on pins
V
CC(n)
; active mode; All V
CC
pins = 5 V;
f
clk(ext)
on pins CLK
(n)
= 5 MHz;
I
CC(1)
= I
CC(2)
= 55 mA;
I
CC(3)
= I
CC(4)
= I
CC(5)
= 2 mA
General
t
deact
t
deb
P
tot
T
amb
[1]
[2]
[3]
[4]
[5]
[6]
[3]
[5]
[5]
Min
Typ
Max
Unit
Card supply voltage pins: V
CC(1)
to V
CC(5)[4]
4.75
2.85
1.71
5
3
1.8
5.25
3.15
1.89
V
V
V
4.65
2.76
1.62
-
-
-
-
-
-
-
-
-
-
-
-
5.35
3.24
1.98
350
55
55
35
116 125
V
V
V
mV
mA
mA
mA
mA
deactivation time
debounce time
total power dissipation
ambient temperature
total sequence
T
amb
=
25 C
to +85
C
[6]
60
-
-
25
80
17.8
455
+25
100
23.8
665
+85
s
ms
mW
C
Refer to
Section 8.6
for further information about the DC-to-DC converter operation.
Typical value measurement based on a 85 % DC-to-DC converter and inductance efficiency; depends on PCB layout and external
component quality (inductor, capacitor).
Maximum value measurement based on a 125 mA (sum of all card supply currents on pins V
CC(n)
) current load and a 75 % DC-to-DC
converter and inductance efficiency; depends on PCB layout and external component quality (inductor, capacitor).
Two ceramic multilayer 100 nF (minimum) capacitors with a low Equivalent Series Resistance (ESR) should be used to meet these
specifications.
Output voltage to the card including ripple.
Refer to
Section 8.8.3
for further information.
TDA8026_1
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1.1 — 30 June 2016
3 of 61
NXP Semiconductors
TDA8026
Multiple smart card slot interface IC
5. Ordering information
The TDA8026 is available in 2 versions. All version have the same functionality. The C3
version is compliant with EMVC0 4.3
Table 2.
Ordering information
Package
Name
TDA8026ET/C2
TDA8026ET/C3
TFBGA64
TFBGA64
Description
plastic thin fine-pitch ball grid array package; 64 balls
plastic thin fine-pitch ball grid array package; 64 balls
Version
SOT1073-1
SOT1073-1
Type number
TDA8026_1
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1.1 — 30 June 2016
4 of 61
NXP Semiconductors
TDA8026
Multiple smart card slot interface IC
6. Block diagram
V
DD
V
DD(INTREGD)
GNDP
GND2 to GND10
LX
H4
V
UP
H5
D3 to D5,E4,E5,
F3 to F5, H8
SEQUENCER
STEP UP
CONVERTER
V
CC
GENERATOR
RST BUFFER
CLK BUFFER
I/O BUFFER
I/O BUFFER
I/O BUFFER
G3
V
CC(1)
RST
(1)
CLK
(1)
I/O
(1)
C4(
1)
C8
(1)
PRES
(1)
GNDC
(1)
V
DD(INTF)
B4
A4
PORADJ
DCDC_OFF
SDWNN
V
DD(INTF)
A8
B8
A5
A4
POWER
MANAGEMENT
UNIT
A7
A6
G4
G2
F2
E3
G1
F1
SCL
SDA
IRQN
A0
INTAUXN
I/OUC1
I/OUC2
CLKIN1
CLKIN2
SPRES
TESTMODE
INHIB
B2
C2
E2
SEQUENCER
E1
D2
C4
C5
C3
B3
H1
A3
H7
SEQUENCER
V
CC
GENERATOR
RST BUFFER
CLK BUFFER
I/O BUFFER
D1
C1
B1
A1
A2
C7
B7
B6
B5
SEQUENCER
V
CC
GENERATOR
RST BUFFER
CLK BUFFER
I/O BUFFER
D7
C6
D6
D8
SEQUENCER
V
CC
GENERATOR
RST BUFFER
CLK BUFFER
I/O BUFFER
E7
E6
F6
C8
E8
INTERFACE
AND
CONTROL
UNIT
V
CC
GENERATOR
RST BUFFER
CLK BUFFER
I/O BUFFER
PRES
DETECTION
G5
PRES
DETECTION
H2
H3
TDA8026
V
CC(2)
RST
(2)
CLK
(2)
I/O
(2)
PRES
(2)
GNDC
(2)
G6
G7
F7
F8
G8
GNDS
STAP5
STAP3
TST1
STAP4
TST2
RST
(5)
I/O
(5)
CLK
(5)
V
CC(5)
I/O
(4)
RST
(4)
CLK
(4)
V
CC(4)
I/O
(3)
RST
(3)
CLK
(3)
V
CC(3)
001aal083
Fig 1.
TDA8026 Block diagram
TDA8026_1
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2016. All rights reserved.
Product data sheet
Rev. 1.1 — 30 June 2016
5 of 61
京公网安备 11010802033920号
EEWORLD
