SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64 bytes of transmit
and receive FIFOs, IrDA SIR built-in support
Rev. 9 — 22 March 2012
Product data sheet
1. General description
The SC16IS752/SC16IS762 is an I
2
C-bus/SPI bus interface to a dual-channel high
performance UART offering data rates up to 5 Mbit/s, low operating and sleeping current;
it also provides the application with 8 additional programmable I/O pins. The device
comes in very small HVQFN32 and TSSOP28 packages, which makes it ideally suitable
for hand-held, battery-operated applications. This chip enables seamless protocol
conversion from I
2
C-bus/SPI to RS-232/RS-485 and is fully bidirectional.
The SC16IS762 differs from the SC16IS752 in that it supports SPI clock speeds up to
15 Mbit/s instead of the 4 Mbit/s supported by the SC16IS752, and in that it supports IrDA
SIR up to 1.152 Mbit/s. In all other aspects, the SC16IS762 is functionally and electrically
the same as the SC16IS752.
The SC16IS752/SC16IS762’s internal register set is backward compatible with the widely
used and widely popular 16C450. This allows the software to be easily written or ported
from another platform.
The SC16IS752/SC16IS762 also provides additional advanced features such as auto
hardware and software flow control, automatic RS-485 support and software reset. This
allows the software to reset the UART at any moment, independent of the hardware reset
signal.
2. Features and benefits
2.1 General features
Dual full-duplex UART
I
2
C-bus or SPI interface selectable
3.3 V or 2.5 V operation
Industrial temperature range:
40 C
to +95
C
64 bytes FIFO (transmitter and receiver)
Fully compatible with industrial standard 16C450 and equivalent
Baud rates up to 5 Mbit/s in 16 clock mode
Auto hardware flow control using RTS/CTS
Auto software flow control with programmable Xon/Xoff characters
Single or double Xon/Xoff characters
Automatic RS-485 support (automatic slave address detection)
Up to eight programmable I/O pins
RS-485 driver direction control via RTS signal
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
RS-485 driver direction control inversion
Built-in IrDA encoder and decoder supporting IrDA SIR with speeds up to 115.2 kbit/s
SC16IS762 supports IrDA SIR with speeds up to 1.152 Mbit/s
1
Software reset
Transmitter and receiver can be enabled/disabled independent of each other
Receive and Transmit FIFO levels
Programmable special character detection
Fully programmable character formatting
5-bit, 6-bit, 7-bit or 8-bit character
Even, odd, or no parity
1, 1
1
⁄
2
, or 2 stop bits
Line break generation and detection
Internal Loopback mode
Sleep current less than 30
A
at 3.3 V
Industrial and commercial temperature ranges
5 V tolerant inputs
Available in HVQFN32 and TSSOP28 packages
2.2 I
2
C-bus features
Noise filter on SCL/SDA inputs
400 kbit/s (maximum)
Compliant with I
2
C-bus Fast mode
Slave mode only
2.3 SPI features
SC16IS752 supports 4 Mbit/s maximum SPI clock speed
SC16IS762 supports 15 Mbit/s maximum SPI clock speed
Slave mode only
SPI Mode 0
3. Applications
Factory automation and process control
Portable and battery operated devices
Cellular data devices
1.
Please note that IrDA SIR at 1.152 Mbit/s is
not
compatible with IrDA MIR at that speed. Please refer to application notes for
usage of IrDA SIR at 1.152 Mbit/s.
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
SC16IS752_SC16IS762
Product data sheet
Rev. 9 — 22 March 2012
2 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
4. Ordering information
Table 1.
Ordering information
Package
Name
SC16IS752IPW
SC16IS762IPW
SC16IS752IBS
SC16IS762IBS
HVQFN32
plastic thermal enhanced very thin quad flat package; no leads; 32 terminals;
body 5
5
0.85 mm
SOT617-1
TSSOP28
Description
plastic thin shrink small outline package; 28 leads; body width 4.4 mm
Version
SOT361-1
Type number
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
3 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
5. Block diagram
V
DD
V
SS
SC16IS752/
SC16IS762
16C450
COMPATIBLE
REGISTER
SETS
TXA
RXA
RTSA
CTSA
TXB
RXB
RTSB
CTSB
SDA
SCL
A0
A1
V
DD
1 kΩ (3.3 V)
1.5 kΩ (2.5 V)
I
2
C-BUS
GPIO7/RIA
GPIO6/CDA
GPIO5/DTRA
GPIO4/DSRA
GPIO3/RIB
GPIO2/CDB
GPIO1/DTRB
GPIO0/DSRB
002aab207
IRQ
RESET
V
DD
I2C/SPI
GPIO
REGISTER
XTAL1
XTAL2
a. I
2
C-bus interface
V
DD
V
SS
SC16IS752/
SC16IS762
16C450
COMPATIBLE
REGISTER
SETS
TXA
RXA
RTSA
CTSA
TXB
RXB
RTSB
CTSB
SCLK
CS
SO
SI
V
DD
1 kΩ (3.3 V)
1.5 kΩ (2.5 V)
SPI
IRQ
RESET
I2C/SPI
GPIO
REGISTER
GPIO7/RIA
GPIO6/CDA
GPIO5/DTRA
GPIO4/DSRA
GPIO3/RIB
GPIO2/CDB
GPIO1/DTRB
GPIO0/DSRB
002aab598
XTAL1
XTAL2
b. SPI interface
Fig 1.
SC16IS752_SC16IS762
Block diagram of SC16IS752/SC16IS762
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
4 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I
2
C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
6. Pinning information
6.1 Pinning
RTSA
CTSA
TXA
RXA
RESET
XTAL1
XTAL2
V
DD
I2C
1
2
3
4
5
6
7
8
9
28 GPIO7/RIA
27 GPIO6/CDA
26 GPIO5/DTRA
25 GPIO4/DSRA
24 RXB
23 TXB
22 V
SS
21 GPIO3/RIB
20 GPIO2/CDB
19 GPIO1/DTRB
18 GPIO0/DSRB
17 RTSB
16 CTSB
15 IRQ
002aab657
RTSA
CTSA
TXA
RXA
RESET
XTAL1
XTAL2
V
DD
SPI
1
2
3
4
5
6
7
8
9
28 GPIO7/RIA
27 GPIO6/CDA
26 GPIO5/DTRA
25 GPIO4/DSRA
24 RXB
23 TXB
22 V
SS
21 GPIO3/RIB
20 GPIO2/CDB
19 GPIO1/DTRB
18 GPIO0/DSRB
17 RTSB
16 CTSB
15 IRQ
002aab599
SC16IS752IPW
SC16IS762IPW
SC16IS752IPW
SC16IS762IPW
A0 10
A1 11
n.c. 12
SCL 13
SDA 14
CS 10
SI 11
SO 12
SCLK 13
V
SS
14
a. I
2
C-bus interface
Fig 2.
Pin configuration for TSSOP28
b. SPI interface
25 GPIO5/DTRA
terminal 1
index area
RXA
RESET
XTAL1
XTAL2
V
DD
I2C
A0
A1
1
2
3
4
5
6
7
8
terminal 1
index area
24 GPIO4/DSRA
23 RXB
22 TXB
21 V
SS
20 GPIO3/RIB
19 GPIO2/CDB
18 GPIO1/DTRB
17 GPIO0/DSRB
RXA
RESET
XTAL1
XTAL2
V
DD
SPI
CS
SI
1
2
3
4
5
6
7
8
25 GPIO5/DTRA
24 GPIO4/DSRA
23 RXB
22 TXB
21 V
SS
20 GPIO3/RIB
19 GPIO2/CDB
18 GPIO1/DTRB
17 GPIO0/DSRB
RTSB 16
002aab208
© NXP B.V. 2012. All rights reserved.
26 GPIO6/CDA
SC16IS752IBS
SC16IS762IBS
SC16IS752IBS
SC16IS762IBS
SCL 10
SDA 11
V
SS
12
V
DD
13
IRQ 14
CTSB 15
RTSB 16
SCLK 10
V
SS
11
V
SS
12
V
DD
13
IRQ 14
002aab658
Transparent top view
Transparent top view
a. I
2
C-bus interface
Fig 3.
Pin configuration for HVQFN32
b. SPI interface
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 9 — 22 March 2012
CTSB 15
9
n.c.
SO
9
26 GPIO6/CDA
27 GPIO7/RIA
27 GPIO7/RIA
31 CTSA
30 RTSA
31 CTSA
30 RTSA
32 TXA
32 TXA
28 V
DD
28 V
DD
29 V
SS
29 V
SS
5 of 60
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