TFF11142HN
Low phase noise LO generator for VSAT applications
Rev. 1 — 28 March 2013
Product data sheet
1. General description
The TFF11142HN is a K
u
band frequency generator intended for low phase noise Local
Oscillator (LO) circuits for K
u
band VSAT transmitters and transceivers. The specified
phase noise complies with IESS-308 from Intelsat.
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Therefore care should be taken
during transport and handling.
2. Features and benefits
Phase noise compliant with IESS-308 (Intelsat) in combination with appropriate source
LO generator with VCO range from 14.13 GHz to 14.42 GHz
Input signal 55 MHz to 901 MHz
Divider settings 16, 32, 64, 128 or 256
Output level
6
dBm; stability
2
dB
Third or fourth order PLL
Internally stabilized voltage references for loop filter
3. Applications
VSAT up converters
Local oscillator signal generation
4. Quick reference data
Table 1.
Quick reference data
Operating conditions of
Table 10
apply.
Symbol
V
CC
I
CC
f
o(RF)
n(synth)
RL
out
Parameter
supply voltage
supply current
RF output frequency
synthesizer phase noise
output return loss
divider value = 64; at 100 kHz offset; reference
phase noise is
149
dBc/Hz at 100 kHz offset
measured at demo board and de-embedded to
footprint
Conditions
Min
3.0
-
-
-
-
Typ Max
3.3
3.6
100 130
97 92
10
-
-
70
Unit
V
mA
dBc/Hz
dB
dBc
14.13 -
14.42 GHz
sup(sp)ref
reference spurious suppression measured at divider value = 256
NXP Semiconductors
TFF11142HN
Low phase noise LO generator for VSAT applications
5. Ordering information
Table 2.
Ordering information
Package
Name
TFF11142HN
HVQFN24
Description
plastic thermal enhanced very thin quad flat package;
no leads; 24 terminals; body 4
4
0.85 mm
Version
SOT616-1
Type number
6. Marking
Table 3.
Marking codes
Marking code
T142
Type number
TFF11142HN
7. Block diagram
NSL2
6
100 kΩ
pull up
NSL1
5
100 kΩ
pull up
NSL0
4
100 kΩ
pull up
VTUNE
3
CPOUT
2
VREGVCO
1
10 pF
LCKDET
7
lock: 2.5 V
no lock: 0 V
100 kΩ
pull down
V
CC(DIV)
(3.3 V)
WINDOW
DETECTOR
30 pF
2.7 V
24
GND3(BUF)
GND1(REF)
8
V
CC(BUF)
RBUF_N
50
Ω
RBUF_P
50
Ω
23
BUF2_P
IN(REF)_P
9
PFD
CP
VCO
CPOUT
VTUNE
22
BUF1_P
DIVIDER
IN(REF)_N
10
NSL0
NSL1
NSL2
11
20
21
BUF2_N
GND2(REF)
BUF1_N
V
CC(REF)
12
19
GND2(BUF)
13
V
CC(DIV)
14
GND(DIV)
15
n.c.
16
n.c.
17
18
001aal724
GND1(BUF) V
CC(BUF)
Fig 1.
Block diagram
TFF11142HN
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 28 March 2013
2 of 17
NXP Semiconductors
TFF11142HN
Low phase noise LO generator for VSAT applications
8. Functional diagram
NSL2
6
NSL1
5
NSL0
4
VTUNE
3
30 pF
CPOUT
VREGVCO
1
2
10 pF
LCKDET
7
lock: 2.5 V
no lock: 0 V
LOCK
DETECTOR
2.7 V
24
GND3(BUF)
GND1(REF)
8
23
BUF2_P
IN(REF)_P
9
PFD
CP
VCO
CPOUT
VTUNE
OUTPUT
BUFFER
22
BUF1_P
DIVIDER
IN(REF)_N
10
NSL0
NSL1
NSL2
20
21
BUF2_N
PLL
GND2(REF)
11
BUF1_N
V
CC(REF)
12
19
GND2(BUF)
13
V
CC(DIV)
14
GND(DIV)
15
n.c.
16
n.c.
17
18
001aal725
GND1(BUF) V
CC(BUF)
Fig 2.
Functional diagram
TFF11142HN
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 28 March 2013
3 of 17
NXP Semiconductors
TFF11142HN
Low phase noise LO generator for VSAT applications
9. Pinning information
9.1 Pinning
24 GND3(BUF)
19 GND2(BUF)
18 V
CC(BUF)
17 GND1(BUF)
16 n.c.
15 n.c.
14 GND(DIV)
13 V
CC(DIV)
IN(REF)_N 10
GND2(REF) 11
V
CC(REF)
12
7
8
9
001aal726
21 BUF2_N
terminal 1
index area
VREGVCO
CPOUT
VTUNE
NSL0
NSL1
NSL2
1
2
3
4
5
6
LCKDET
Transparent top view
Fig 3.
Pin configuration for HVQFN24
9.2 Pin description
Table 4.
Symbol
VREGVCO
CPOUT
VTUNE
NSL0
NSL1
NSL2
LCKDET
IN(REF)_P
IN(REF)_N
V
CC(REF)
V
CC(DIV)
GND(DIV)
n.c.
n.c.
Pin description
Pin Description
1
2
3
4
5
6
7
9
10
12
13
14
15
16
Regulated output voltage for VCO loop filter. Connect loop filter to this pin.
Charge pump output.
Tuning voltage for VCO.
Divider setting, LSB. Leave open for “1”, connect to GND for “0”. See
Table 8.
Divider setting. Leave open for “1”, connect to GND for “0”. See
Table 8.
Divider setting, MSB. Leave open for “1”, connect to GND for “0”. See
Table 8.
Lock detect. Lock = 2.5 V; out of lock = 0 V. See
Table 6.
Ground for REF input. Connect this pin to the exposed diepad landing.
Reference signal, non-inverting input. Couple this AC to the source.
Reference signal, inverting input. Couple this AC to the source.
Ground for REF input. Connect this pin to the exposed diepad landing.
Supply of the internal regulated voltages. Decouple this pin against
GND2(REF) (pin 11).
Supply of the divider and PFD/CP. Decouple this pin against GND(DIV)
(pin 14).
Ground of the divider. Connect this pin to the exposed diepad landing.
not connected
not connected
Ground for RF output. Connect this pin to the exposed diepad landing.
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
GND1(REF) 8
GND2(REF) 11
GND1(BUF) 17
TFF11142HN
Product data sheet
Rev. 1 — 28 March 2013
GND1(REF)
IN(REF)_P
20 BUF1_N
23 BUF2_P
22 BUF1_P
4 of 17
NXP Semiconductors
TFF11142HN
Low phase noise LO generator for VSAT applications
Pin description
…continued
Pin Description
18
Supply voltage for the RF output buffer. Decouple this pin against GND2(BUF)
(pin 19).
Ground for RF output. Connect this pin to the exposed diepad landing.
RF output.
RF output.
RF output.
RF output.
Ground for RF output. Connect this pin to the exposed diepad landing.
Table 4.
Symbol
V
CC(BUF)
GND2(BUF) 19
BUF1_N
BUF2_N
BUF1_P
BUF2_P
20
21
22
23
GND3(BUF) 24
10. Functional description
The TFF11142HN consists of the following blocks:
•
•
•
•
•
PLL
Output buffer
Lock detector
Reference input
Divider settings
The functionality of the blocks will be discussed below.
10.1 PLL
The PLL is formed by the VCO, DIVIDER (possible settings: 16, 32, 64, 128 and 256
(see
Table 8))
and a PFD/CP. The tune voltage is referred to the band gap regulated
voltage: VREGVCO (pin 1).
The loop filter can be set to type 2 or type 3. If a type 2 filter is used, the pins
CPOUT (pin 2) and VTUNE (pin 3) must be interconnected. A 10 pF capacitor is placed
internally between pins CPOUT (pin 2) and VREGVCO (pin 1), and a 30 pF capacitor is
placed between pins VTUNE (pin 3) and VREGVCO (pin 1). See
Figure 4
and
Figure 5.
Values for the loop filter components are given in
Table 5.
The VCO input voltage range is between 0.1 and 0.9 V
O(reg)VCO
.
TFF11142HN
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 28 March 2013
5 of 17
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