Features
•
Single 3.3V
±
10% Supply
•
Fast Read Access Time – 200 ns
•
Automatic Page Write Operation
– Internal Address and Data Latches for 128 Bytes
– Internal Control Timer
Fast Write Cycle Time
– Page Write Cycle Time – 10 ms Maximum
– 1 to 128-Byte Page Write Operation
Low Power Dissipation
– 15 mA Active Current
– 20 µA CMOS Standby Current
Hardware and Software Data Protection
DATA Polling for End of Write Detection
High Reliability CMOS Technology
– Endurance: 10
5
Cycles
– Data Retention: 10 Years
JEDEC Approved Byte-Wide Pinout
Industrial Temperature Range
Green (Pb/Halide-free) Packaging Option Only
•
•
•
•
•
•
•
•
1-Megabit
(128K x 8)
Low Voltage
Paged Parallel
EEPROMs
AT28LV010
1. Description
The AT28LV010 is a high-performance 3-volt only Electrically Erasable and Program-
mable Read-Only Memory. Its 1 megabit of memory is organized as 131,072 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 200 ns with power dissipation of just 54 mW. When the device
is deselected, the CMOS standby current is less than 20 µA.
The AT28LV010 is accessed like a Static RAM for the read or write cycle without the
need for external components. The device contains a 128-byte page register to allow
writing of up to 128 bytes simultaneously. During a write cycle, the address and 1 to
128 bytes of data are internally latched, freeing the address and data bus for other
operations. Following the initiation of a write cycle, the device will automatically write
the latched data using an internal control timer. The end of a write cycle can be
detected by DATA polling of I/O7. Once the end of a write cycle has been detected a
new access for a read or write can begin.
Atmel’s 28LV010 has additional features to ensure high quality and manufacturability.
The device utilizes internal error correction for extended endurance and improved
data retention characteristics. Software data protection is implemented to guard
against inadvertent writes. The device also includes an extra 128 bytes of EEPROM
for device identification or tracking.
0395F–PEEPR–08/09
AT28LV010
2. Pin Configurations
Pin Name
A0 - A16
CE
OE
WE
I/O0 - I/O7
NC
DC
Function
Addresses
Chip Enable
Output Enable
Write Enable
Data Inputs/Outputs
No Connect
Don’t Connect
2.2
A11
A9
A8
A13
A14
NC
WE
VCC
NC
A16
A15
A12
A7
A6
A5
A4
32-lead TSOP Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
I/O7
I/O6
I/O5
I/O4
I/O3
GND
I/O2
I/O1
I/O0
A0
A1
A2
A3
2.1
32-lead PLCC Top View
A12
A15
A16
DC
VCC
WE
NC
I/O1
I/O2
GND
I/O3
I/O4
I/O5
I/O6
14
15
16
17
18
19
20
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
5
6
7
8
9
10
11
12
13
4
3
2
1
32
31
30
29
28
27
26
25
24
23
22
21
A14
A13
A8
A9
A11
OE
A10
CE
I/O7
2
0395F–PEEPR–08/09
AT28LV010
3. Block Diagram
4. Device Operation
4.1
Read
The AT28LV010 is accessed like a Static RAM. When CE and OE are low and WE is high, the
data stored at the memory location determined by the address pins is asserted on the outputs.
The outputs are put in the high impedance state when either CE or OE is high. This dual-line
control gives designers flexibility in preventing bus contention in their system.
4.2
Write
The write operation of the AT28LV010 allows 1 to 128 bytes of data to be written into the
device during a single internal programming period. Each write operation must be preceded by
the software data protection (SDP) command sequence. This sequence is a series of three
unique write command operations that enable the internal write circuitry. The command
sequence and the data to be written must conform to the software protected write cycle timing.
Addresses are latched on the falling edge of WE or CE, whichever occurs last and data is
latched on the rising edge of WE or CE, whichever occurs first. Each successive byte must be
written within 150 µs (t
BLC
) of the previous byte. If the t
BLC
limit is exceeded the AT28LV010
will cease accepting data and commence the internal programming operation. If more than
one data byte is to be written during a single programming operation, they must reside on the
same page as defined by the state of the A7 - A16 inputs. For each WE high to low transition
during the page write operation, A7 - A16 must be the same.
The A0 to A6 inputs are used to specify which bytes within the page are to be written. The
bytes may be loaded in any order and may be altered within the same load period. Only bytes
which are specified for writing will be written; unnecessary cycling of other bytes within the
page does not occur.
3
0395F–PEEPR–08/09
4.3
DATA Polling
The AT28LV010 features DATA Polling to indicate the end of a write cycle. During a byte or
page write cycle an attempted read of the last byte written will result in the complement of the
written data to be presented on I/O7. Once the write cycle has been completed, true data is
valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime
during the write cycle.
4.4
Toggle Bit
In addition to DATA Polling the AT28LV010 provides another method for determining the end
of a write cycle. During the write operation, successive attempts to read data from the device
will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop
toggling and valid data will be read. Reading the toggle bit may begin at any time during the
write cycle.
4.5
Data Protection
If precautions are not taken, inadvertent writes may occur during transitions of the host system
power supply. Atmel
®
has incorporated both hardware and software features that will protect
the memory against inadvertent writes.
4.5.1
Hardware Protection
Hardware features protect against inadvertent writes to the AT28LV010 in the following ways:
(a) V
CC
power-on delay – once V
CC
has reached 2.0V (typical) the device will automatically
time out 5 ms (typical) before allowing a write; (b) write inhibit – holding any one of OE low, CE
high or WE high inhibits write cycles; and (c) noise filter – pulses of less than 15 ns (typical) on
the WE or CE inputs will not initiate a write cycle.
Software Data Protection
The AT28LV010 incorporates the industry standard software data protection (SDP) function.
Unlike standard 5-volt only EEPROM’s, the AT28LV010 has SDP enabled at all times. There-
fore, all write operations must be preceded by the SDP command sequence.
The data in the 3-byte command sequence is not written to the device; the addresses in the
command sequence can be utilized just like any other location in the device. Any attempt to
write to the device without the 3-byte sequence will start the internal timers. No data will be
written to the device. However, for the duration of t
WC
, read operations will effectively be poll-
ing operations.
4.5.2
4
AT28LV010
0395F–PEEPR–08/09
AT28LV010
5. DC and AC Operating Range
AT28LV010-20
Operating
Temperature (Case)
V
CC
Power Supply
Ind.
-40°C - 85°C
3.3V
±
5%
AT28LV010-25
-40°C - 85°C
3.3V
±
10%
6. Operating Modes
Mode
Read
Write
(2)
Standby/Write Inhibit
Write Inhibit
Write Inhibit
Output Disable
Notes:
1. X can be V
IL
or V
IH
.
2. Refer to AC Programming Waveforms.
CE
V
IL
V
IL
V
IH
X
X
X
OE
V
IL
V
IH
X
(1)
X
V
IL
V
IH
WE
V
IH
V
IL
X
V
IH
X
X
High Z
I/O
D
OUT
D
IN
High Z
7. Absolute Maximum Ratings*
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
All Input Voltages (including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to V
CC
+ 0.6V
Voltage on OE and A9
with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
8. DC Characteristics
Symbol
I
LI
I
LO
I
SB
I
CC
V
IL
V
IH
V
OL
V
OH
Parameter
Input Load Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Active Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
I
OL
= 1.6 mA; V
CC
= 3.0V
I
OH
= -100
μA;
V
CC
= 3.0V
2.4
2.0
0.45
Condition
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
CE = V
CC
- 0.3V to V
CC
+ 1V
Ind.
Min
Max
1
1
50
15
0.8
Units
µA
µA
µA
mA
V
V
V
V
f = 5 MHz; I
OUT
= 0 mA; V
CC
= 3.6V
5
0395F–PEEPR–08/09
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