PHD101NQ03LT
N-channel TrenchMOS logic level FET
Rev. 5 — 31 October 2011
Product data sheet
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
1.2 Features and benefits
Low conduction losses due to low
on-state resistance
Simple gate drive required due to low
gate charge
Suitable for logic level gate drive
sources
1.3 Applications
DC-to-DC converters
1.4 Quick reference data
Table 1.
Symbol
V
DS
I
D
P
tot
R
DSon
Quick reference data
Parameter
drain-source voltage
drain current
total power dissipation
drain-source on-state
resistance
gate-drain charge
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
mb
= 25 °C; V
GS
= 10 V; see
Figure 1;
see
Figure 3
T
mb
= 25 °C; see
Figure 2
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
see
Figure 9;
see
Figure 10
V
GS
= 5 V; I
D
= 50 A; V
DS
= 15 V;
T
j
= 25 °C; see
Figure 11
Min
-
-
-
-
Typ
-
-
-
4.5
Max
30
75
166
5.5
Unit
V
A
W
mΩ
Static characteristics
Dynamic characteristics
Q
GD
-
8
-
nC
Nexperia
PHD101NQ03LT
N-channel TrenchMOS logic level FET
2. Pinning information
Table 2.
Pin
1
2
3
mb
Pinning information
Symbol Description
G
D
S
D
gate
drain
[1]
source
mounting base; connected to drain
mbb076
Simplified outline
mb
Graphic symbol
D
G
S
2
1
3
SOT428 (DPAK)
[1]
It is not possible to make a connection to pin 2.
3. Ordering information
Table 3.
Ordering information
Package
Name
PHD101NQ03LT
DPAK
Description
plastic single-ended surface-mounted package (DPAK); 3 leads
(one lead cropped)
Version
SOT428
Type number
4. Limiting values
Table 4.
Symbol
V
DS
V
DGR
V
GS
I
D
Limiting values
Parameter
drain-source voltage
drain-gate voltage
gate-source voltage
drain current
V
GS
= 10 V; T
mb
= 100 °C; see
Figure 1
V
GS
= 10 V; T
mb
= 25 °C; see
Figure 1;
see
Figure 3
I
DM
P
tot
T
stg
T
j
V
GSM
I
S
I
SM
E
DS(AL)S
peak drain current
total power dissipation
storage temperature
junction temperature
peak gate-source voltage
source current
peak source current
non-repetitive drain-source
avalanche energy
pulsed;
δ
= 25 %; t
p
≤
50 µs
T
mb
= 25 °C
pulsed; t
p
≤
10 µs; T
mb
= 25 °C
V
GS
= 10 V; T
j(init)
= 25 °C; I
D
= 43 A;
V
sup
≤
15 V; unclamped; t
p
= 0.19 ms;
R
GS
= 50
Ω
pulsed; t
p
≤
10 µs; T
mb
= 25 °C; see
Figure 3
T
mb
= 25 °C; see
Figure 2
Conditions
T
j
≥
25 °C; T
j
≤
175 °C
T
j
≥
25 °C; T
j
≤
175 °C; R
GS
= 20 kΩ
Min
-
-
-20
-
-
-
-
-55
-55
-25
-
-
-
Max
30
30
20
75
75
240
166
175
175
25
75
240
185
Unit
V
V
V
A
A
A
W
°C
°C
V
A
A
mJ
In accordance with the Absolute Maximum Rating System (IEC 60134).
Source-drain diode
Avalanche ruggedness
PHD101NQ03LT
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 31 October 2011
2 of 13
Nexperia
PHD101NQ03LT
N-channel TrenchMOS logic level FET
120
I
der
(%)
80
03ai19
120
P
der
(%)
80
03aa16
40
40
0
0
50
100
150
200
T
mb
(°C)
0
0
50
100
150
T
mb
(°C)
200
Fig 1.
Normalized continuous drain current as a
function of mounting base temperature
Fig 2.
Normalized total power dissipation as a
function of mounting base temperature
03ai21
10
3
I
D
(A)
Limit R
DSon
= V
DS
/ I
D
t
p
= 10
µ
s
100
µ
s
10
2
DC
10
1 ms
10 ms
1
1
10
V
DS
(V)
10
2
Fig 3.
Safe operating area; continuous and peak drain currents as a function of drain-source voltage
PHD101NQ03LT
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 31 October 2011
3 of 13
Nexperia
PHD101NQ03LT
N-channel TrenchMOS logic level FET
5. Thermal characteristics
Table 5.
Symbol
R
th(j-mb)
R
th(j-a)
Thermal characteristics
Parameter
thermal resistance from junction to
mounting base
thermal resistance from junction to
ambient
Conditions
see
Figure 4
minimum footprint
SOT404 minimum footprint
[1]
[1]
Min
-
-
-
Typ
-
75
50
Max
0.9
-
-
Unit
K/W
K/W
K/W
[1]
Mounted on a printed-circuit board; vertical in still air.
10
Z
th(j-mb)
(K/W)
1
δ
= 0.5
0.2
10
-1
0.1
0.05
0.02
10
-2
single pulse
t
p
T
P
03ai20
δ
=
t
p
T
t
10
-3
10
-5
10
-4
10
-3
10
-2
10
-1
t
p
(s)
1
Fig 4.
Transient thermal impedance from junction to mounting base as a function of pulse duration
PHD101NQ03LT
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 31 October 2011
4 of 13
Nexperia
PHD101NQ03LT
N-channel TrenchMOS logic level FET
6. Characteristics
Table 6.
Symbol
V
(BR)DSS
V
GS(th)
Characteristics
Parameter
drain-source breakdown
voltage
gate-source threshold voltage
Conditions
I
D
= 250 µA; V
GS
= 0 V; T
j
= -55 °C
I
D
= 250 µA; V
GS
= 0 V; T
j
= 25 °C
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 175 °C;
see
Figure 7;
see
Figure 8
I
D
= 1 mA; V
DS
= V
GS
; T
j
= -55 °C;
see
Figure 7;
see
Figure 8
I
D
= 1 mA; V
DS
= V
GS
; T
j
= 25 °C;
see
Figure 7;
see
Figure 8
I
DSS
I
GSS
R
DSon
drain leakage current
gate leakage current
drain-source on-state
resistance
V
DS
= 30 V; V
GS
= 0 V; T
j
= 25 °C
V
DS
= 30 V; V
GS
= 0 V; T
j
= 175 °C
V
GS
= 20 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= -20 V; V
DS
= 0 V; T
j
= 25 °C
V
GS
= 10 V; I
D
= 25 A; T
j
= 25 °C;
see
Figure 9;
see
Figure 10
V
GS
= 5 V; I
D
= 25 A; T
j
= 175 °C;
see
Figure 9;
see
Figure 10
V
GS
= 5 V; I
D
= 25 A; T
j
= 25 °C;
see
Figure 9;
see
Figure 10
Dynamic characteristics
Q
G(tot)
Q
GS
Q
GD
C
iss
C
oss
C
rss
t
d(on)
t
r
t
d(off)
t
f
V
SD
t
rr
Q
r
total gate charge
gate-source charge
gate-drain charge
input capacitance
output capacitance
reverse transfer capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain voltage
reverse recovery time
recovered charge
I
S
= 25 A; V
GS
= 0 V; T
j
= 25 °C;
see
Figure 13
I
S
= 10 A; dI
S
/dt = -100 A/µs;
V
GS
= 0 V; V
DS
= 25 V; T
j
= 25 °C
V
DS
= 15 V; R
L
= 0.6
Ω;
V
GS
= 4.5 V;
R
G(ext)
= 5.6
Ω;
T
j
= 25 °C; I
D
= 25 A
V
DS
= 25 V; V
GS
= 0 V; f = 1 MHz;
T
j
= 25 °C; see
Figure 12
I
D
= 50 A; V
DS
= 15 V; V
GS
= 5 V;
T
j
= 25 °C; see
Figure 11
-
-
-
-
-
-
-
-
-
-
-
-
-
23
10.5
8
2180
600
225
23
90
37
33
0.85
37
33
-
-
-
-
-
-
-
-
-
-
1.2
-
-
nC
nC
nC
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
Min
27
30
0.6
-
1
-
-
-
-
-
-
-
Typ
-
-
-
-
1.9
0.05
-
10
10
4.5
10.5
5.8
Max
-
-
-
2.9
2.5
1
500
100
100
5.5
13.5
7.5
Unit
V
V
V
V
V
µA
µA
nA
nA
mΩ
mΩ
mΩ
Static characteristics
Source-drain diode
PHD101NQ03LT
All information provided in this document is subject to legal disclaimers.
©
Nexperia B.V. 2017. All rights reserved
Product data sheet
Rev. 5 — 31 October 2011
5 of 13
京公网安备 11010802033920号
EEWORLD
