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DM74ALS540AWMX

Description
Bus Driver, ALS Series, 1-Func, 8-Bit, Inverted Output, TTL, PDSO20, 0.300 INCH, MS-013, SOIC-20
Categorylogic   
File Size61KB,5 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
Environmental Compliance
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DM74ALS540AWMX Overview

Bus Driver, ALS Series, 1-Func, 8-Bit, Inverted Output, TTL, PDSO20, 0.300 INCH, MS-013, SOIC-20

DM74ALS540AWMX Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerFairchild
Parts packaging codeSOIC
package instruction0.300 INCH, MS-013, SOIC-20
Contacts20
Reach Compliance Codeunknown
Is SamacsysN
Control typeENABLE LOW
seriesALS
JESD-30 codeR-PDSO-G20
JESD-609 codee3
length12.8 mm
Load capacitance (CL)50 pF
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.024 A
Humidity sensitivity level1
Number of digits8
Number of functions1
Number of ports2
Number of terminals20
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Output polarityINVERTED
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP20,.4
Package shapeRECTANGULAR
Package formSMALL OUTLINE
method of packingTAPE AND REEL
Peak Reflow Temperature (Celsius)260
power supply5 V
Maximum supply current (ICC)22 mA
Prop。Delay @ Nom-Sup12 ns
propagation delay (tpd)12 ns
Certification statusNot Qualified
Maximum seat height2.65 mm
Maximum supply voltage (Vsup)5.5 V
Minimum supply voltage (Vsup)4.5 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.5 mm
Base Number Matches1
DM74ALS540A Octal Inverting Buffer and Line Driver with 3-STATE Outputs
October 1986
Revised February 2000
DM74ALS540A
Octal Inverting Buffer and Line Driver
with 3-STATE Outputs
General Description
This octal buffer and line driver is designed to have the per-
formance of the DM74ALS240A series and, at the same
time, offer a pinout with inputs and outputs on opposite
sides of the package. This arrangement greatly enhances
printed circuit board layout. The 3-STATE control gate is a
2-input NOR such that if either G1 or G2 is HIGH, all eight
outputs are in the high impedance state.
Features
s
Advanced oxide-isolated, ion-implanted Schottky TTL
process
s
Switching performance is guaranteed over full tempera-
ture and V
CC
supply range
s
Data flow-thru pinout (All inputs on opposite side from
outputs)
s
P-N-P inputs reduce DC loading
Ordering Code:
Order Number
DM74ALS540AWM
DM74ALS540ASJ
DM74ALS540AN
Package Number Package Description
M20B
M20D
N20A
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
G1
H
X
L
L
G2
X
H
L
L
A
X
X
L
H
Output
Y
Hi-Z
Hi-Z
H
L
H
=
HIGH Logic Level
L
=
LOW Logic Level
X
=
Don't Care (Either HIGH or LOW Logic Level)
Hi-Z
=
High Impedance (OFF) State
© 2000 Fairchild Semiconductor Corporation
DS009170
www.fairchildsemi.com
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