DS1000
5-Tap Silicon Delay Line
www.dalsemi.com
FEATURES
All-silicon time delay
5 taps equally spaced
Delays are stable and precise
Both leading and trailing edge accuracy
Delay tolerance
±5%
or
±2
ns, whichever is
greater
Low-power CMOS
TTL/CMOS-compatible
Vapor phase, IR and wave solderable
Custom delays available
Fast turn prototypes
Extended temperature range available
(DS1000-IND)
IN
NC
NC
TAP 2
NC
TAP 4
GND
PIN ASSIGNMENT
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
NC
TAP 1
TAP 4
NC
GND
TAP 3
NC
TAP 5
1
2
3
4
8
7
6
5
V
CC
TAP 1
TAP 3
TAP 5
4
5
TAP 5
3
6
TAP 3
IN
TAP 2
1
2
8
7
V
CC
TAP 1
DS1000M 8-Pin DIP (300-mil)
See Mech. Drawings Section
IN
DS1000 14-Pin DIP (300-mil)
See Mech. Drawings Section
TAP 2
TAP 4
GND
DS1000Z 8-Pin SOIC (150-mil)
See Mech. Drawings Section
PIN DESCRIPTION
TAP 1-TAP 5
V
CC
GND
NC
IN
- TAP Output Number
- +5 Volts
- Ground
- No Connection
- Input
DESCRIPTION
The DS1000 series delay lines have five equally spaced taps providing delays from 4 ns to 500 ns. These
devices are offered in a standard 14-pin DIP that is pin-compatible with hybrid delay lines. Alternatively,
8-pin DIPs and surface mount packages are available to save PC board area. Low cost and superior
reliability over hybrid technology is achieved by the combination of a 100% silicon delay line and
industry standard DIP and SOIC packaging. In order to maintain complete pin compatibility, DIP
packages are available with hybrid lead configurations. The DS1000 series delay lines provide a nominal
accuracy of
±5%
or
±2
ns, whichever is greater. The DS1000 5-Tap Silicon Delay Line reproduces the
input logic state at the output after a fixed delay as specified by the extension of the part number after the
dash. The DS1000 is designed to reproduce both leading and trailing edges with equal precision. Each
tap is capable of driving up to ten 74LS loads. Dallas Semiconductor can customize standard products to
meet special needs. For special requests and rapid delivery, call 972-371-4348.
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111799
DS1000
LOGIC DIAGRAM
Figure 1
DS1000
PART NUMBER DELAY TABLE (all values in ns)
Table 1
PART #
DS1000-
Nom
4
5
6
7
8
9
10
12
15
20
25
30
35
40
50
100
-20
-25
-30
-35
-40
-45
-50
-60
-75
-100
-125
-150
-175
-200
-250
-500
TAP 1
TOLERANCE
Init
Temp
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1.1
2
1.2
2.5
1.5
5
3
Nom
8
10
12
14
16
18
20
24
30
40
50
60
70
80
100
200
TAP 2
TOLERANCE
Init
Temp
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1.2
2.5
1.5
3
1.8
3.5
2.1
4
2.4
5
3
10
6
Nom
12
15
18
21
24
27
30
36
45
60
75
90
105
120
150
300
TAP 3
TOLERANCE
Init
Temp
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1.1
2.3
1.4
3
1.8
3.8
2.3
4.5
2.7
5.3
3.2
6
3.6
7.5
4.5
15
9
Nom
16
20
24
28
32
36
40
48
60
80
100
120
140
160
200
400
TAP 4
TOLERANCE
Init
Temp
2
1
2
1
2
1
2
1
2
1
2
1.1
2
1.2
2.4
1.5
3
1.8
4
2.4
5
3
6
3.6
7
4.2
8
4.8
10
6
20
12
Nom
20
25
30
35
40
45
50
60
75
100
125
150
175
200
250
500
TAP 5
TOLERANCE
Init
Temp
2
1
2
1
2
1
2
1.1
2
1.2
2.3
1.4
2.5
1.5
3
1.8
3.8
2.3
5
3
6.3
3.8
7.5
4.5
8.8
5.3
10
6
12.5
7.5
25
15
DC ELECTRICAL CHARACTERISTICS
PARAMETER
Supply Voltage
High Level Input
Voltage
Low Level Input
Voltage
Input Leakage
Current
Active Current
High Level Output
Current
Low Level Output
Current
SYM
V
CC
V
IH
V
IL
I
I
I
CC
I
OH
I
OL
0.0V
≤
V
I
≤
V
CC
V
CC
=Max;
Period=Min.
V
CC
=Min.
V
OH
=4
V
CC
=Min.
V
OL
=0.5
TEST
CONDITION
MIN
4.75
2.2
-0.5
-1.0
(0°C to 70°C; V
CC
= 5.0V ± 5%)
TYP
5.00
MAX
5.25
V
CC
+ 0.5
0.8
1.0
35
75
-1
12
UNITS
V
V
V
uA
mA
mA
mA
7, 9
NOTES
6
6
6
AC ELECTRICAL CHARACTERISTICS
PARAMETER
Input Pulse Width
Input to Tap Delay
(leading edge)
Input to Tap Delay
(trailing edge)
Power-up Time
Input Period
SYMBOL
t
WI
t
PLH
t
PHL
t
PU
Period
MIN
40% of Tap 5 t
PLH
(T
A
= 25°C; V
CC
= 5V ± 5%)
TYP
Table 1
Table 1
100
MAX
UNITS
ns
ns
ns
ms
ns
NOTES
8
1, 2, 3, 4,
5, 10
1, 2, 3, 4,
5, 10
8
4 (t
WI
)
2 of 5
DS1000
CAPACITANCE
PARAMETER
Input Capacitance
SYMBOL
C
IN
MIN
TYP
5
MAX
10
(T
A
= 25°C)
UNITS
pF
NOTES
NOTES:
1. Initial tolerances are
±=with
respect to the nominal value at 25°C and 5V.
2. Temperature tolerance is
±=with
respect to the initial delay value over a range of 0°C to 70°C.
3. The delay will also vary with supply voltage, typically by less than 4% over the range 4.75 to 5.25V.
4. All tap delays tend to vary uni-directionally with temperature or voltage changes. For example, if
TAP 1 slows down, all other taps also slow down; TAP3 can never be faster than TAP2.
5. Intermediate delay values and packaging variations are available on a custom basis. For further
information, call 972-371–4348.
6. All voltages are referenced to ground.
7. Measured with outputs open.
8. Pulse width and period specifications may be exceeded; however, accuracy may be impaired
depending on application (decoupling, layout, etc.). The device will remain functional with pulse
widths down to 20% of Tap 5 delay, and input periods as short as 2(t
WI
).
9. I
CC
is a function of frequency and TAP 5 delay. Only a -25 operating with a 40-ns period and V
CC
=
5.25V will have an I
CC
= 75 mA. For example a -100 will never exceed 30 mA, etc.
10. See “Test Conditions” section at the end of this data sheet.
TIMING DIAGRAM: SILICON DELAY LINE
Figure 2
3 of 5
DS1000
TEST CIRCUIT
Figure 3
TERMINOLOGY
Period:
The time elapsed between the leading edge of the first pulse and the leading edge of the
following pulse.
t
WI
(Pulse Width):
The elapsed time on the pulse between the 1.5V point on the leading edge and the
1.5V point on the trailing edge or the 1.5V point on the trailing edge and the 1.5V point on the leading
edge.
t
RISE
(Input Rise Time):
The elapsed time between the 20% and the 80% point on the leading edge of the
input pulse.
t
FALL
(Input Fall Time):
The elapsed time between the 80% and the 20% point on the trailing edge of the
input pulse.
t
PLH
(Time Delay, Rising):
The elapsed time between the 1.5V point on the leading edge of the input
pulse and the 1.5V point on the leading edge of any tap output pulse.
t
PHL
(Time Delay, Falling):
The elapsed time between the 1.5V point on the trailing edge of the input
pulse and the 1.5V point on the trailing edge of any tap output pulse.
TEST SETUP DESCRIPTION
Figure 3 illustrates the hardware configuration used for measuring the timing parameters on the DS1000.
The input waveform is produced by a precision pulse generator under software control. Time delays are
measured by a time interval counter (20 ps resolution) connected between the input and each tap. Each
tap is selected and connected to the counter by a VHF switch control unit. All measurements are fully
automated, with each instrument controlled by a central computer over an IEEE 488 bus.
4 of 5
DS1000
TEST CONDITIONS
INPUT:
Ambient Temperature:
Supply Voltage (V
CC
):
Input Pulse:
Source Impedance:
Rise and Fall Time:
Pulse Width:
Period:
25°C
±=3°C
5.0V
±=0.1V
High = 3.0V
±=0.1V
Low = 0.0V
±=0.1V
50 ohm Max.
3.0 ns Max. (measured between 0.6V and 2.4V)
500 ns (1
µs
for -500)
1
µs
(2
µs
for -500)
OUTPUT:
Each output is loaded with the equivalent of one 74F04 input gate. Delay is measured at the 1.5V level on
the rising and falling edge.
NOTE:
Above conditions are for test only and do not restrict the operation of the device under other data sheet
conditions.
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