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80HCPS1616CHMG

Description
IC SER RAPIDIO SWITCH 400FCBGA
Categorysemiconductor    Other integrated circuit (IC)   
File Size980KB,77 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Environmental Compliance
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80HCPS1616CHMG Overview

IC SER RAPIDIO SWITCH 400FCBGA

80HCPS1616CHMG Parametric

Parameter NameAttribute value
typeSerial RapidIO® Switch
applicationwireless infrastructure
Installation typesurface mount
Package/casing400-BBGA,FCBGA
Supplier device packaging400-FCBGA(21x21)
16-Port, 16-Lane, 80Gbps,
Gen2 RapidIO Switch
CPS-1616
Datasheet
Description
The CPS-1616 (80HCPS1616) is a
RapidIO Specification (Rev. 2.1)
compliant Central Packet Switch whose functionality is central to
routing packets for distribution among DSPs, processors, FPGAs,
other switches, or any other RapidIO-based devices. It can also be
used in RapidIO backplane switching. The CPS-1616 supports Serial
RapidIO (S-RIO) packet switching (unicast, multicast, and an optional
broadcast) from any of its 16input ports to any of its 16 output ports.
Features
• RapidIO ports
— 16 bidirectional S-RIO lanes
— Port widths of 1x, 2x, and 4x allow up to 20 Gbps per port
— Port speeds selectable: 6.25, 5, 3.125, 2.5, or 1.25 Gbaud
— Support Level I defined short or long haul reach, and Level II
defined short-, medium-, or long-run reach for each PHY speed
— Error Management Extensions support
— Software-assisted error recovery, supporting hot swap
• I
2
C Interfaces
— Provides I
2
C port for maintenance and error reporting
— Master or Slave operation
— Master allows power-on configuration from external ROM
— Master mode configuration with external image compressing and
checksum
• Switch
— 80 Gbps peak throughput
— Non-blocking data flow architecture
— Configurable for Cut-Through or Store-and-Forward data flow
— Very low latency for all packet lengths and load conditions
— Internal queuing buffer and retransmit buffer
— Standard transmitter- or receiver-controlled flow control
— Global routing or Local Port routing capability
— Supports up to 40 simultaneous multicast masks, with broadcast
— Performance monitoring counters for performance and
diagnostics analysis. Per input port and output port counters
• SerDes
— Transmitter pre-emphasis and drive strength + receiver
equalization provides best possible signal integrity
— Embedded PRBS generation and detection with programmable
polynomials support Bit Error Rate testing
• Additional Information
— Packet Trace/Mirror. Each input port can copy all incoming
packets matching user-defined criteria to a “trace” output port.
— Packet Filter. Each input port can filter (drop) all incoming packets
matching user-defined criteria.
— Device configurable through any of S-RIO ports, I
2
C, or JTAG
— Full JTAG Boundary Scan Support (IEEE1149.1 and 1149.6)
Lidded/Lidless
784-FCBGA Package: 21

21 mm, 1.0 mm ball
pitch
Block Diagram
Quadrant 0
Lanes 0-3
Ports 0-3
Quadrant 3
Lanes 12-15
Ports 12-15
CPS-1616
RapidIO Gen2
Switch Fabric
Event Management and Maintenance
Registers
I
2
C Controller
Ports 4-7
Lanes 4-7
Quadrant 1
JTAG Controller
Ports 8-11
Lanes 8-11
Quadrant 2
Typical Applications
High-performance computing
Wireless
Defense and aerospace
Video and imaging
©2017 Integrated Device Technology, Inc.
1
June 26, 2017

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Description IC SER RAPIDIO SWITCH 400FCBGA IC SER RAPIDIO SWITCH 400FCBGA IC SER RAPIDIO SWITCH 400FCBGA
type Serial RapidIO® Switch Serial RapidIO® Switch Serial RapidIO® Switch
application wireless infrastructure wireless infrastructure wireless infrastructure
Installation type surface mount surface mount surface mount
Package/casing 400-BBGA,FCBGA 400-BBGA,FCBGA 400-BBGA,FCBGA
Supplier device packaging 400-FCBGA(21x21) 400-FCBGA(21x21) 400-FCBGA(21x21)
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