80HCPS1616CHMG8 datasheet, PDF

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80HCPS1616CHMG8: DescriptionIC SER RAPIDIO SWITCH 400FCBGA; Categorysemiconductor Other integrated circuit (IC); File Size980KB，77 Pages; ManufacturerIDT (Integrated Device Technology, Inc.); Websitehttp://www.idt.com/; Environmental Compliance

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80HCPS1616CHMG8 Overview

IC SER RAPIDIO SWITCH 400FCBGA

80HCPS1616CHMG8 Parametric

Parameter Name	Attribute value
type	Serial RapidIO® Switch
application	wireless infrastructure
Installation type	surface mount
Package/casing	400-BBGA，FCBGA
Supplier device packaging	400-FCBGA（21x21）

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16-Port, 16-Lane, 80Gbps,

Gen2 RapidIO Switch

CPS-1616

Datasheet

Description

The CPS-1616 (80HCPS1616) is a

RapidIO Specification (Rev. 2.1)

compliant Central Packet Switch whose functionality is central to

routing packets for distribution among DSPs, processors, FPGAs,

other switches, or any other RapidIO-based devices. It can also be

used in RapidIO backplane switching. The CPS-1616 supports Serial

RapidIO (S-RIO) packet switching (unicast, multicast, and an optional

broadcast) from any of its 16input ports to any of its 16 output ports.

Features

• RapidIO ports

— 16 bidirectional S-RIO lanes

— Port widths of 1x, 2x, and 4x allow up to 20 Gbps per port

— Port speeds selectable: 6.25, 5, 3.125, 2.5, or 1.25 Gbaud

— Support Level I defined short or long haul reach, and Level II

defined short-, medium-, or long-run reach for each PHY speed

— Error Management Extensions support

— Software-assisted error recovery, supporting hot swap

• I

C Interfaces

— Provides I

C port for maintenance and error reporting

— Master or Slave operation

— Master allows power-on configuration from external ROM

— Master mode configuration with external image compressing and

checksum

• Switch

— 80 Gbps peak throughput

— Non-blocking data flow architecture

— Configurable for Cut-Through or Store-and-Forward data flow

— Very low latency for all packet lengths and load conditions

— Internal queuing buffer and retransmit buffer

— Standard transmitter- or receiver-controlled flow control

— Global routing or Local Port routing capability

— Supports up to 40 simultaneous multicast masks, with broadcast

— Performance monitoring counters for performance and

diagnostics analysis. Per input port and output port counters

• SerDes

— Transmitter pre-emphasis and drive strength + receiver

equalization provides best possible signal integrity

— Embedded PRBS generation and detection with programmable

polynomials support Bit Error Rate testing

• Additional Information

— Packet Trace/Mirror. Each input port can copy all incoming

packets matching user-defined criteria to a “trace” output port.

— Packet Filter. Each input port can filter (drop) all incoming packets

matching user-defined criteria.

— Device configurable through any of S-RIO ports, I

C, or JTAG

— Full JTAG Boundary Scan Support (IEEE1149.1 and 1149.6)

—

Lidded/Lidless

784-FCBGA Package: 21



21 mm, 1.0 mm ball

pitch

Block Diagram

Quadrant 0

Lanes 0-3

Ports 0-3

Quadrant 3

Lanes 12-15

Ports 12-15

CPS-1616

RapidIO Gen2

Switch Fabric

Event Management and Maintenance

Registers

C Controller

Ports 4-7

Lanes 4-7

Quadrant 1

JTAG Controller

Ports 8-11

Lanes 8-11

Quadrant 2

Typical Applications

•

High-performance computing

Wireless

Defense and aerospace

Video and imaging

June 26, 2017

CPS-1616 Datasheet

Table of Contents

About This Document.................................................................................................................... 4

Introduction............................................................................................................................................................................................................ 4

Additional Resources............................................................................................................................................................................................. 4

Document Conventions and Definitions................................................................................................................................................................. 4

Revision History..................................................................................................................................................................................................... 4

Device Description ........................................................................................................................ 6

Specification Compliancy....................................................................................................................................................................................... 7

Functional Overview ..................................................................................................................... 7

Interface Overview........................................................................................................................ 8

S-RIO Ports ........................................................................................................................................................................................................... 8

I2C Bus .................................................................................................................................................................................................................. 8

JTAG TAP Port...................................................................................................................................................................................................... 8

Interrupt (IRQ_N) ................................................................................................................................................................................................... 8

Reset (RST_N) ...................................................................................................................................................................................................... 8

Clock (REF_CLK_P/N) .......................................................................................................................................................................................... 8

Rext (REXT_N/P) .................................................................................................................................................................................................. 9

Speed Select (SPD[2:0])........................................................................................................................................................................................ 9

Quadrant Config (QCFG[7:0])................................................................................................................................................................................ 9

Port Disable (PD[15:0]_N) ..................................................................................................................................................................................... 9

Frequency Select (FSEL[1:0]) ............................................................................................................................................................................... 9

Multicast (MCAST)................................................................................................................................................................................................. 9

Configuration Pins ....................................................................................................................... 10

Speed Select Pins SPD[2:0]................................................................................................................................................................................ 10

Quadrant Configuration Pins QCFG[7:0]............................................................................................................................................................. 10

Absolute Maximum Ratings ........................................................................................................ 14

Recommended Operating Conditions ......................................................................................... 15

AC Test Conditions...................................................................................................................... 16

Power Consumption .................................................................................................................... 18

10. I

C Bus ......................................................................................................................................... 18

C Master Mode and Slave Mode....................................................................................................................................................................... 19

C Device Address ............................................................................................................................................................................................. 19

Signaling.............................................................................................................................................................................................................. 19

Read/Write Figures.............................................................................................................................................................................................. 20

C DC Electrical Specifications........................................................................................................................................................................... 22

C AC Electrical Specifications........................................................................................................................................................................... 24

C Timing Waveforms......................................................................................................................................................................................... 25

11. Interrupt (IRQ_N) Electrical Specifications ................................................................................ 26

12. Configuration (Static) Pin Specification ..................................................................................... 27

13. S-RIO Ports .................................................................................................................................. 28

Overview.............................................................................................................................................................................................................. 28

Definition of Amplitude and Swing....................................................................................................................................................................... 29

1.25, 2.5, and 3.125 Gbaud LP-Serial Links........................................................................................................................................................ 30

Level I Electrical Specification ............................................................................................................................................................................. 30

5 and 6.25 Gbaud LP-Serial Links....................................................................................................................................................................... 37

Level II Electrical Specifications .......................................................................................................................................................................... 37

June 26, 2017

CPS-1616 Datasheet

14. Reference Clock .......................................................................................................................... 47

Reference Clock Electrical Specifications ........................................................................................................................................................... 47

15. Reset (RST_N) Specification ....................................................................................................... 49

16. JTAG Interface ............................................................................................................................ 50

Description........................................................................................................................................................................................................... 50

IEEE 1149.1 (JTAG) and IEEE 1149.6 (AC Extest) Compliance ........................................................................................................................ 50

System Logic TAP Controller Overview............................................................................................................................................................... 50

Signal Definitions ................................................................................................................................................................................................. 51

Test Data Register (DR) ...................................................................................................................................................................................... 52

Boundary Scan Registers.................................................................................................................................................................................... 52

Instruction Register (IR)....................................................................................................................................................................................... 55

EXTEST............................................................................................................................................................................................................... 56

Configuration Register Access ............................................................................................................................................................................ 58

JTAG DC Electrical Specifications....................................................................................................................................................................... 59

JTAG AC Electrical Specifications....................................................................................................................................................................... 60

JTAG Timing Waveforms..................................................................................................................................................................................... 61

17. Pinout and Pin Listing ................................................................................................................. 62

Pinout — Top View .............................................................................................................................................................................................. 62

Pin Listing ............................................................................................................................................................................................................ 63

18. Package Specifications .............................................................................................................. 69

Package Physical Specifications ......................................................................................................................................................................... 69

Package Outline Drawings .................................................................................................................................................................................. 69

Thermal Characteristics....................................................................................................................................................................................... 74

19. Ordering Information ................................................................................................................... 76

June 26, 2017

80HCPS1616CHMG8 Related Products

	80HCPS1616CHMG8	80HCPS1616CHMG	80HCPS1616CHMGI8
Description	IC SER RAPIDIO SWITCH 400FCBGA	IC SER RAPIDIO SWITCH 400FCBGA	IC SER RAPIDIO SWITCH 400FCBGA
type	Serial RapidIO® Switch	Serial RapidIO® Switch	Serial RapidIO® Switch
application	wireless infrastructure	wireless infrastructure	wireless infrastructure
Installation type	surface mount	surface mount	surface mount
Package/casing	400-BBGA，FCBGA	400-BBGA，FCBGA	400-BBGA，FCBGA
Supplier device packaging	400-FCBGA（21x21）	400-FCBGA（21x21）	400-FCBGA（21x21）

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