Data Sheet
FEATURES
4-Channel, Low Noise, Low Power, 24-Bit,
Sigma-Delta ADC with PGA and Reference
AD7124-4
Low-side power switch
General-purpose outputs
Multiple filter options
Internal temperature sensor
Self and system calibration
Sensor burnout detection
Automatic channel sequencer
Per channel configuration
Power supply: 2.7 V to 3.6 V and ±1.8 V
Independent interface power supply
Power-down current: 5 µA maximum
Temperature range: −40°C to +125°C
32-lead LFCSP/24-lead TSSOP
3-wire or 4-wire serial interface
SPI, QSPI, MICROWIRE, and DSP compatible
Schmitt trigger on SCLK
ESD: 4 kV
3 power modes
RMS noise
Low power: 24 nV rms at 1.17 SPS, gain = 128 (255 µA typical)
Mid power: 20 nV rms at 2.34 SPS, gain = 128 (355 µA typical)
Full power: 23 nV rms at 9.4 SPS, gain = 128 (930 µA typical)
Up to 22 noise free bits in all power modes (gain = 1)
Output data rate
Full power: 9.38 SPS to 19,200 SPS
Mid power: 2.34 SPS to 4800 SPS
Low power: 1.17 SPS to 2400 SPS
Rail-to-rail analog inputs for gains > 1
Simultaneous 50 Hz/60 Hz rejection at 25 SPS (single cycle
settling)
Diagnostic functions (which aid safe integrity level (SIL)
certification)
Crosspoint multiplexed analog inputs
4 differential/7 pseudo differential inputs
Programmable gain (1 to 128)
Band gap reference with 10 ppm/°C drift maximum (70 µA)
Matched programmable excitation currents
Internal clock oscillator
On-chip bias voltage generator
APPLICATIONS
Temperature measurement
Pressure measurement
Industrial process control
Instrumentation
Smart transmitters
FUNCTIONAL BLOCK DIAGRAM
AV
DD
REGCAPA
V
BIAS
CROSSPOINT
MUX
AV
DD
BANDGAP
REF
REFOUT
AV
DD
AV
SS
REFIN1(+) REFIN1(–)
REFIN2(+)
REFIN2(–)
IOV
DD
REGCAPD
1.9V
LDO
AV
SS
1.8V
LDO
AIN0/IOUT/VBIAS
AIN1/IOUT/VBIAS
AIN2/IOUT/VBIAS/P1
AIN3/IOUT/VBIAS/P2
AIN4/IOUT/VBIAS
AIN5/IOUT/VBIAS
AIN6/IOUT/VBIAS/REFIN2(+)
AIN7/IOUT/VBIAS/REFIN2(–)
X-MUX
REFERENCE
BUFFERS
BUF
VARIABLE
DIGITAL
FILTER
SERIAL
INTERFACE
AND
CONTROL
LOGIC
DOUT/RDY
DIN
SCLK
CS
BURNOUT
DETECT
PGA1
PGA2
BUF
24-BIT
Σ-Δ ADC
AV
SS
GPOs
TEMPERATURE
SENSOR
DIAGNOSTICS
AV
DD
EXCITATION
CURRENTS
ANALOG
BUFFERS
CHANNEL
SEQUENCER
SYNC
DIAGNOSTICS
COMMUNICATIONS
POWER SUPPLY
SIGNAL CHAIN
DIGITAL
INTERNAL
CLOCK
PSW
POWER
SWITCH
AV
SS
CLK
AV
SS
DGND
Figure 1.
Rev. D
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13197-001
AD7124-4
AD7124-4
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
General Description ......................................................................... 5
Specifications..................................................................................... 6
Timing Characteristics .............................................................. 11
Absolute Maximum Ratings .......................................................... 14
Thermal Resistance .................................................................... 14
ESD Caution ................................................................................ 14
Pin Configurations and Function Descriptions ......................... 15
Typical Performance Characteristics ........................................... 18
Terminology .................................................................................... 27
RMS Noise and Resolution............................................................ 28
Full Power Mode ......................................................................... 28
Mid Power Mode ........................................................................ 31
Low Power Mode ........................................................................ 34
Getting Started ................................................................................ 37
Overview...................................................................................... 37
Power Supplies ............................................................................ 38
Digital Communication............................................................. 38
Configuration Overview ........................................................... 40
ADC Circuit Information .............................................................. 45
Analog Input Channel ............................................................... 45
External Impedance When Using a Gain of 1 ........................ 46
Programmable Gain Array (PGA) ........................................... 47
Reference ..................................................................................... 47
Bipolar/Unipolar Configuration .............................................. 47
Data Output Coding .................................................................. 48
Excitation Currents .................................................................... 48
Bridge Power-Down Switch ...................................................... 49
Logic Outputs.............................................................................. 49
Bias Voltage Generator .............................................................. 49
Clock ............................................................................................ 49
Power Modes ............................................................................... 49
Standby and Power-Down Modes ............................................ 49
Digital Interface .......................................................................... 50
DATA_STATUS .......................................................................... 52
Serial Interface Reset (DOUT_RDY_DEL and CS_EN Bits) 52
Reset ............................................................................................. 52
Data Sheet
Calibration................................................................................... 53
Span and Offset Limits .............................................................. 54
System Synchronization ............................................................ 54
Digital Filter .................................................................................... 55
Sinc
4
Filter ................................................................................... 55
Sinc
3
Filter ................................................................................... 57
Fast Settling Mode (Sinc
4
+ Sinc
1
Filter) .................................. 59
Fast Settling Mode (Sinc
3
+ Sinc
1
Filter) .................................. 61
Post Filters ................................................................................... 63
Summary of Filter Options ....................................................... 66
Diagnostics ...................................................................................... 67
Signal Chain Check .................................................................... 67
Reference Detect ......................................................................... 67
Calibration, Conversion, and Saturation Errors .................... 67
Overvoltage/Undervoltage Detection ..................................... 67
Power Supply Monitors ............................................................. 68
LDO Monitoring ........................................................................ 68
MCLK Counter ........................................................................... 68
SPI SCLK Counter...................................................................... 68
SPI Read/Write Errors ............................................................... 69
SPI_IGNORE Error ................................................................... 69
Checksum Protection ................................................................ 69
Memory Map Checksum Protection ....................................... 69
ROM Checksum Protection...................................................... 70
Burnout Currents ....................................................................... 71
Temperature Sensor ................................................................... 71
Grounding and Layout .................................................................. 72
Applications Information .............................................................. 73
Temperature Measurement Using a Thermocouple .............. 73
Temperature Measurement Using an RTD ............................. 74
Flowmeter.................................................................................... 76
On-Chip Registers .......................................................................... 78
Communications Register......................................................... 79
Status Register ............................................................................. 79
ADC_CONTROL Register ....................................................... 80
Data Register ............................................................................... 82
IO_CONTROL_1 Register........................................................ 82
IO_CONTROL_2 Register........................................................ 84
ID Register................................................................................... 84
Error Register .............................................................................. 84
Rev. D | Page 2 of 93
Data Sheet
ERROR_EN Register ..................................................................85
MCLK_COUNT Register ..........................................................87
Channel Registers........................................................................87
Configuration Registers .............................................................89
Filter Registers .............................................................................90
AD7124-4
Offset Registers............................................................................ 91
Gain Registers .............................................................................. 91
Outline Dimensions ........................................................................ 92
Ordering Guide ........................................................................... 93
REVISION HISTORY
6/2018—Rev. C to Rev. D
Changes to Features Section ............................................................ 1
Changes to General Description Section ....................................... 5
Added Table 1; Renumbered Sequentially ..................................... 5
Changes to Drift Parameter, External REFIN Voltage Parameter,
and Note 12, Table 3.......................................................................... 8
Changes to Table 7 ..........................................................................16
Changes to Figure 13 and Figure 15 .............................................18
Changes to Figure 44, Figure 45, and Figure 46 ..........................23
Changes to Reference Section........................................................37
Changes to Accessing the ADC Register Map Section and Reset
Column, Table 39 ............................................................................39
Changes to External Impedance When Using a Gain of 1
Section ..............................................................................................46
Changes to Reference Section........................................................47
Changes to Standby and Power-Down Modes Section ..............49
Changes to Calibration Section .....................................................53
Change to Sinc
3
Output Data Rate and Settling Time Section .57
Change to Calibration, Conversion, and Saturation Errors
Section .......................................................................................................... 67
Changes to MCLK Counter Section .............................................68
Changes to Memory Map Checksum Protection Section .........69
Changes to Reset Column and Note 1, Table 64 .........................78
Changes to Description Column, Table 68 ..................................81
Changes to ID Register Section .....................................................84
Changes to Description Column, Table 73 ..................................87
Changes to Description Column, Table 74 ..................................88
Changes to Configuration Registers Section ...............................89
Updated Outline Dimensions ........................................................92
Changes to Ordering Guide ...........................................................93
7/2016—Rev. B to Rev. C
Change to Features Section .............................................................. 1
Changes to Specifications Section and Table 2.............................. 5
Changes to Table 4 ..........................................................................13
Change to Table 8 ............................................................................27
Changes to Table 9 and Table 10 ...................................................28
Change to Table 25 ..........................................................................32
Changes to Table 28 ........................................................................33
Change to Table 29 ..........................................................................34
Changes to Accessing the ADC Register Map and Table 38 .....38
Changes to Diagnostics Section, Table 44, and Table 45 ...........41
Added External Impedance When Using a Gain of 1 Section,
Figure 74, Figure 75, and Figure 76; Renumbered Sequentially .....45
Changes to Standby and Power-Down Modes Section ..............48
Changes to Single Conversion Mode Section ............................. 50
Changes to Continuous Read Mode Section ............................... 51
Changes to Sinc
4
Output Data Rate/Settling Time Section ....... 54
Changes to Sinc
4
Zero Latency Section ........................................ 55
Changes to Sinc
3
Output Data Rate and Settling Time Section ......56
Changes to Sinc
3
Zero Latency Section ........................................ 57
Change to Output Data Rate and Settling Time, Sinc
4
+ Sinc
1
Filter Section .................................................................................... 59
Change to Output Data Rate and Settling Time, Sinc
3
+ Sinc
1
Filter Section .................................................................................... 60
Changes to SPI_IGNORE Error Section ...................................... 68
Added ROM Checksum Protection Section................................ 69
Changes to Table 63 ........................................................................ 77
Changes to ID Register Section and Error Register Section ..... 83
Changes to Table 70 and ERROR_EN Register Section ............ 84
Changes to Table 71 ........................................................................ 85
Changes to Table 73 ........................................................................ 87
12/2015—Rev. A to Rev. B
Changed +105°C to +125°C .........................................Throughout
Changes to Table 2 ............................................................................ 5
Added Endnote 4, Table 2; Renumbered Sequentially ............... 10
Changes to Figure 17 Through Figure 22 .................................... 18
Changes to Figure 23 Through Figure 26 .................................... 19
Changes to Figure 30, Figure 33, and Figure 34 .......................... 20
Changes to Figure 37 Through Figure 40 .................................... 21
Changes to Figure 41 Through Figure 46 .................................... 22
Changes to Figure 47 and Figure 48 ............................................. 23
Changes to Figure 64 ...................................................................... 25
Changes to Figure 126 .................................................................... 69
Change to Table 17 .......................................................................... 30
Changes to Reference Section ....................................................... 36
Changes to Accessing the ADC Register Map Section and
Table 38 ............................................................................................. 38
Change to Table 63 .......................................................................... 76
Change to ID Register Section ...................................................... 82
Change to Table 73 .......................................................................... 85
Change to Table 73 .......................................................................... 86
Changes to the Ordering Guide .................................................... 90
7/2015—Rev. 0 to Rev. A
Change to Data Sheet Title .............................................................. 1
Changes to Internal Reference Drift Parameter, Table 2 ............. 7
Changes to Figure 30 ...................................................................... 20
Change to Digital Outputs Section ............................................... 37
Rev. D | Page 3 of 93
AD7124-4
Change to Single Conversion Mode Section............................... 49
Changes to Calibration Section .................................................... 51
Changes to Figure 83 ...................................................................... 53
Changes to Figure 91 ...................................................................... 56
Changes to Figure 99 ...................................................................... 58
Changes to Figure 105 .................................................................... 60
Data Sheet
Changes to Reference Detect Section and Figure 119 ............... 65
Change to Table 70 ......................................................................... 83
Changes to Table 71 ....................................................................... 84
5/2015—Revision 0: Initial Version
Rev. D | Page 4 of 93
Data Sheet
GENERAL DESCRIPTION
The
AD7124-4
is a low power, low noise, completely integrated
analog front end for high precision measurement applications.
The device contains a low noise, 24-bit Σ-Δ analog-to-digital
converter (ADC), and can be configured to have four differential
inputs or seven single-ended or pseudo differential inputs. The
on-chip low gain stage ensures that signals of small amplitude
can be interfaced directly to the ADC.
One of the major advantages of the
AD7124-4
is that it gives the
user the flexibility to employ one of three integrated power
modes. The current consumption, range of output data rates,
and rms noise can be tailored with the power mode selected.
The device also offers a multitude of filter options, ensuring that
the user has the highest degree of flexibility.
The
AD7124-4
can achieve simultaneous 50 Hz and 60 Hz
rejection when operating at an output data rate of 25 SPS (single
cycle settling), with rejection in excess of 80 dB achieved at lower
output data rates.
The
AD7124-4
establishes the highest degree of signal chain
integration. The device contains a precision, low noise, low
drift internal band gap reference, and also accepts an external
differential reference, which can be internally buffered. Other
key integrated features include programmable low drift excitation
current sources, burnout currents, and a bias voltage generator,
which sets the common-mode voltage of a channel to AV
DD
/2.
The low-side power switch enables the user to power down
bridge sensors between conversions, ensuring the absolute
minimal power consumption of the system. The device also
allows the user the option of operating with either an internal
clock or an external clock.
The integrated channel sequencer allows several channels to be
enabled simultaneously, and the
AD7124-4
sequentially converts
on each enabled channel, simplifying communication with the
Parameter
LFCSP Package Height
Internal Reference Drift
Excitation Currents in Standby Mode
Gain of 1, High Impedance Loads
AD7124-4
device. As many as 16 channels can be enabled at any time; a
channel being defined as an analog input or a diagnostic such as
a power supply check or a reference check. This unique feature
allows diagnostics to be interleaved with conversions. The
AD7124-4
also supports per channel configuration. The device
allows eight configurations or setups. Each configuration
consists of gain, filter type, output data rate, buffering, and
reference source. The user can assign any of these setups on a
channel by channel basis.
The
AD7124-4
also has extensive diagnostic functionality
integrated as part of its comprehensive feature set. These
diagnostics include a cyclic redundancy check (CRC), signal
chain checks, and serial interface checks, which lead to a more
robust solution. These diagnostics reduce the need for external
components to implement diagnostics, resulting in reduced
board space needs, reduced design cycle times, and cost savings.
The failure modes effects and diagnostic analysis (FMEDA) of a
typical application has shown a safe failure fraction (SFF) greater
than 90% according to IEC 61508.
The device operates with a single analog power supply from 2.7 V
to 3.6 V or a dual 1.8 V power supply. The digital supply has a
range of 1.65 V to 3.6 V. It is specified for a temperature range
of −40°C to +125°C. The
AD7124-4
is housed in a 32-lead
LFCSP package and a 24-lead TSSOP package.
Note that, throughout this data sheet, multifunction pins, such
as DOUT/RDY, are referred to either by the entire pin name or
by a single function of the pin, for example, RDY, when only
that function is relevant.
The
AD7124-4
B grade has operational and performance
differences from the
AD7124-4.
Table 1 lists these differences.
Unless otherwise noted, all references to
AD7124-4
refer to the
device and not to the B grade.
AD7124-4
B Grade
0.95 mm
10 ppm/°C
Remain active if enabled
Does not impact settling time when switching channels
Table 1. Differences Between the
AD7124-4
and the
AD7124-4
B Grade
AD7124-4
0.75 mm
15 ppm/°C
Disabled
Impacts settling time when switching channels
Table 2.
AD7124-4
Overview
Parameter
Maximum Output Data Rate
RMS Noise (Gain = 128)
Peak-to-Peak Resolution at 1200 SPS
(Gain = 1)
Typical Current (ADC + PGA)
Low Power Mode
2400 SPS
24 nV
16.4 bits
255 µA
Mid Power Mode
4800 SPS
20 nV
17.1 bits
355 µA
Full Power Mode
19,200 SPS
23 nV
18 bits
930 µA
Rev. D | Page 5 of 93
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