Philips Semiconductors
Preliminary data
XA 16-bit microcontroller family
64K Flash/2K RAM, watchdog, 2 UARTs
XA-G49
GENERAL DESCRIPTION
The XA-G49 is a member of Philips’ 80C51 XA (eXtended
Architecture) family of high performance 16-bit single-chip
microcontrollers.
The XA-G49 contains 64 kbytes of Flash program memory, and
provides three general purpose timers/counters, a watchdog timer,
dual UARTs, and four general purpose I/O ports with programmable
output configurations.
A default serial loader program in the Boot ROM allows In-System
Programming (ISP) of the Flash memory without the need for a
loader in the Flash code. User programs may erase and reprogram
the Flash memory at will through the use of standard routines
contained in the Boot ROM (In-Application Programming).
•
Single supply voltage In-System Programming (ISP) of the Flash
•
Boot ROM contains low level Flash programming routines for
In-Application Programming and a default serial loader using the
UART
memory (V
PP
= V
DD
, or V
PP
= 12 V if desired)
•
2048 bytes of on-chip data RAM
•
Supports off-chip program and data addressing up to 1 megabyte
(20 address lines)
•
Three standard counter/timers with enhanced features (same as
XA-G3 T0, T1, and T2). All timers have a toggle output capability
FEATURES
•
64 kbytes of on-chip Flash program memory with In-System
Programming capability
•
Watchdog timer
•
Two enhanced UARTs with independent baud rates
•
Seven software interrupts
•
Four 8-bit I/O ports, with 4 programmable output configurations for
each pin
•
Five Flash blocks = two 8 kbyte blocks and three 16 kbyte blocks
•
Nearly identical to XA-G3, except for double the program and
RAM memories
•
30 MHz operating frequency at 5 V
•
Power saving operating modes: Idle and Power-Down.
Wake-Up from power-down via an external interrupt is supported.
•
44-pin PLCC and 44-pin LQFP packages
BLOCK DIAGRAM
XA CPU Core
Program
Memory
Bus
64K Bytes
FLASH
Data
Bus
SFR
bus
UART 0
2048 Bytes
Static RAM
Port 0
Port 1
UART 1
Timer 0, 1
Timer 2
Port 2
Port 3
Watchdog
Timer
SU01002
2001 Jun 27
2
Philips Semiconductors
Preliminary data
XA 16-bit microcontroller family
64K Flash/2K RAM, watchdog, 2 UARTs
XA-G49
PIN DESCRIPTIONS
PIN. NO.
MNEMONIC
LCC
V
SS
V
DD
P0.0 – P0.7
1, 22
23, 44
43–36
LQFP
16
17
37–30
I
I
I/O
Ground:
0 V reference.
Power Supply:
This is the power supply voltage for normal, idle, and power down operation.
Port 0:
Port 0 is an 8-bit I/O port with a user-configurable output type. Port 0 latches have 1s
written to them and are configured in the quasi-bidirectional mode during reset. The operation of
port 0 pins as inputs and outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to the section on I/O port configuration and the DC Electrical
Characteristics for details.
When the external program/data bus is used, Port 0 becomes the multiplexed low data/instruction
byte and address lines 4 through 11.
P1.0 – P1.7
2–9
40–44,
1–3
I/O
Port 1:
Port 1 is an 8-bit I/O port with a user-configurable output type. Port 1 latches have 1s
written to them and are configured in the quasi-bidirectional mode during reset. The operation of
port 1 pins as inputs and outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to the section on I/O port configuration and the DC Electrical
Characteristics for details.
Port 1 also provides special functions as described below.
A0/WRH:
Address bit 0 of the external address bus when the external data bus is
configured for an 8 bit width. When the external data bus is configured for a 16
bit width, this pin becomes the high byte write strobe.
A1:
Address bit 1 of the external address bus.
A2:
Address bit 2 of the external address bus.
A3:
Address bit 3 of the external address bus.
RxD1 (P1.4):
Receiver input for serial port 1.
TxD1 (P1.5):
Transmitter output for serial port 1.
T2 (P1.6):
Timer/counter 2 external count input/clockout.
T2EX (P1.7):
Timer/counter 2 reload/capture/direction control
Port 2:
Port 2 is an 8-bit I/O port with a user-configurable output type. Port 2 latches have 1s
written to them and are configured in the quasi-bidirectional mode during reset. The operation of
port 2 pins as inputs and outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to the section on I/O port configuration and the DC Electrical
Characteristics for details.
When the external program/data bus is used in 16-bit mode, Port 2 becomes the multiplexed high
data/instruction byte and address lines 12 through 19. When the external program/data bus is used in
8-bit mode, the number of address lines that appear on port 2 is user programmable.
P3.0 – P3.7
11,
13–19
5,
7–13
I/O
Port 3:
Port 3 is an 8-bit I/O port with a user configurable output type. Port 3 latches have 1s
written to them and are configured in the quasi-bidirectional mode during reset. the operation of
port 3 pins as inputs and outputs depends upon the port configuration selected. Each port pin is
configured independently. Refer to the section on I/O port configuration and the DC Electrical
Characteristics for details.
Port 3 also provides various special functions as described below.
RxD0 (P3.0):
Receiver input for serial port 0.
TxD0 (P3.1):
Transmitter output for serial port 0.
INT0 (P3.2):
External interrupt 0 input.
INT1 (P3.3):
External interrupt 1 input.
T0 (P3.4):
Timer 0 external input, or timer 0 overflow output.
T1/BUSW (P3.5):
Timer 1 external input, or timer 1 overflow output. The value on this pin is
latched as the external reset input is released and defines the default
external data bus width (BUSW). 0 = 8-bit bus and 1 = 16-bit bus.
WRL (P3.6):
External data memory low byte write strobe.
RD (P3.7):
External data memory read strobe.
Reset:
A low on this pin resets the microcontroller, causing I/O ports and peripherals to take on
their default states, and the processor to begin execution at the address contained in the reset
vector. Refer to the section on Reset for details.
Address Latch Enable:
A high output on the ALE pin signals external circuitry to latch the address
portion of the multiplexed address/data bus. A pulse on ALE occurs only when it is needed in order
to process a bus cycle.
TYPE
NAME AND FUNCTION
2
40
O
3
4
5
6
7
8
9
P2.0 – P2.7
24–31
41
42
43
44
1
2
3
18–25
O
O
O
I
O
I/O
I
I/O
11
13
14
15
16
17
5
7
8
9
10
11
I
O
I
I
I/O
I/O
18
19
RST
10
12
13
4
O
O
I
ALE
33
27
I/O
2001 Jun 27
5
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