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EPF10K130EFC484-1X

Description
IC FPGA 369 I/O 484FBGA
CategoryProgrammable logic devices    Programmable logic   
File Size2MB,182 Pages
ManufacturerIntel
Websitehttp://www.intel.com/
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EPF10K130EFC484-1X Overview

IC FPGA 369 I/O 484FBGA

EPF10K130EFC484-1X Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerIntel
package instructionBGA, BGA484,22X22,40
Reach Compliance Codecompliant
ECCN code3A991
JESD-30 codeS-PBGA-B484
JESD-609 codee0
length23 mm
Humidity sensitivity level3
Number of I/O lines369
Number of entries369
Number of logical units6656
Output times369
Number of terminals484
Maximum operating temperature70 °C
Minimum operating temperature
organize369 I/O
Output functionMIXED
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA484,22X22,40
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)220
power supply2.5,2.5/3.3 V
Programmable logic typeLOADABLE PLD
propagation delay0.3 ns
Certification statusNot Qualified
Maximum seat height2.1 mm
Maximum supply voltage2.625 V
Minimum supply voltage2.375 V
Nominal supply voltage2.5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperature30
width23 mm
Package Information Datasheet for
Mature Altera Devices
DS-PKG-16.8
This datasheet provides package and thermal resistance information for mature
Altera
®
devices. Package information includes the ordering code reference, package
acronym, leadframe material, lead finish (plating), JEDEC outline reference, lead
coplanarity, weight, moisture sensitivity level, and other special information. The
thermal resistance information includes device pin count, package name, and
resistance values.
This datasheet includes the following sections:
“Device and Package Cross Reference” on page 1
“Thermal Resistance” on page 23
“Package Outlines” on page 44
f
For more package and thermal resistance information about Altera devices that are
not listed in this datasheet, refer to the
Package and Thermal Resistance
page of the
Altera website.
For information about trays, tubes, and dry packs, refer to
AN 71: Guidelines for
Handling J-Lead, QFP, and BGA Devices.
RoHS-compliant devices are compatible with leaded-reflow temperatures. For more
information, refer to
Altera’s RoHS-Compliant Devices
literature page.
f
f
Device and Package Cross Reference
Table 2
through
Table 22
lists the device, package type, and number of pins for each
Altera device listed in this datasheet. Altera devices listed in this datasheet are
available in the following packages:
Ball-Grid Array (BGA)
Ceramic Pin-Grid Array (PGA)
FineLine BGA (FBGA)
Hybrid FineLine BGA (HBGA)
Plastic Dual In-Line Package (PDIP)
Plastic Enhanced Quad Flat Pack (EQFP)
Plastic J-Lead Chip Carrier (PLCC)
Plastic Quad Flat Pack (PQFP)
Power Quad Flat Pack (RQFP)
Thin Quad Flat Pack (TQFP)
Ultra FineLine BGA (UBGA)
© December 2011
Altera Corporation
Package Information Datasheet for Mature Altera Devices
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Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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