Freescale Semiconductor
Data Sheet
Document Number: MSC7110
Rev. 11, 4/2008
MSC7110
Low-Cost 16-bit DSP with
DDR Controller
MAP-BGA–400
17 mm
×
17 mm
• StarCore
®
SC1400 DSP extended core with one SC1400 DSP
core, 64 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte
instruction cache (ICache), four-entry write buffer, programmable
interrupt controller (PIC), and low-power Wait and Stop
processing modes.
• 8 Kbyte boot ROM.
• AHB-Lite crossbar switch that allows parallel data transfers
between four master ports and six slave ports, where each port
connects to an AHB-Lite bus; fixed or round robin priority
programmable at each slave port; programmable bus parking at
each slave port; low power mode.
• Internal PLL generates up to 266 MHz clock for the SC1400 core
and up to 133 MHz for the crossbar switch, DMA channels, and
other peripherals.
• Clock synthesis module provides predivision of PLL input clock;
independent clocking of the internal timers and DDR module;
programmable operation in the SC1400 low power Stop mode;
independent shutdown of different regions of the device.
• Enhanced 16-bit wide host interface (HDI16) provides a glueless
connection to industry-standard microcomputers,
microprocessors, and DSPs and can also operate with an 8-bit host
data bus, making if fully compatible with the DSP56300 HI08
from the external host side.
• DDR memory controller that supports byte enables for up to a
32-bit data bus; glueless interface to 133 MHz 14-bit page mode
DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;
and 16-bit or 32-bit external data bus.
• Programmable memory interface with independent read buffers,
programmable predictive read feature for each buffer, and a write
buffer.
• System control unit performs software watchdog timer function;
includes programmable bus time-out monitors on AHB-Lite slave
buses; includes bus error detection and programmable time-out
monitors on AHB-Lite master buses; and has address
out-of-range detection on each crossbar switch buses.
• Event port collects and counts important signal events including
DMA and interrupt requests and trigger events such as interrupts,
breakpoints, DMA transfers, or wake-up events; units operate
independently, in sequence, or triggered externally; can be used
standalone or with the OCE10.
• Multi-channel DMA controller with 32 time-multiplexed
unidirectional channels, priority-based time-multiplexing
between channels using 32 internal priority levels, fixed- or
round-robin-priority operation, major-minor loop structure, and
DONE or DRACK protocol from requesting units.
• One TDM module with independent receive and transmit,
programmable sharing of frame sync and clock, programmable
word size (8 or 16-bit), hardware-base A-law/μ-law conversion,
up to 50 Mbps data rate, up to 128 channels, with glueless
interface to E1/T1 frames and MVIP, SCAS, and H.110 buses.
• UART with full-duplex operation up to 5.0 Mbps.
• Up to 41 general-purpose input/output (GPIO) ports.
• I
2
C interface that allows booting from EEPROM devices up to 1
Mbyte.
• Two quad timer modules, each with sixteen configurable 16-bit
timers.
• fieldBIST™ unit detects and provides visibility into unlikely field
failures for systems with high availability to ensure structural
integrity, that the device operates at the rated speed, is free from
reliability defects, and reports diagnostics for partial or complete
device inoperability.
• Standard JTAG interface allows easy integration to system
firmware and internal on-chip emulation (OCE10) module.
• Optional booting external host via 8-bit or 16-bit access through
the HDI16, I
2
C, or SPI using in the boot ROM to access serial SPI
Flash/EEPROM devices; different clocking options during boot
with the PLL on or off using a variety of input frequency ranges.
© Freescale Semiconductor, Inc., 2004, 2008. All rights reserved.
Table of Contents
1
2
Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
1.1 MAP-BGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .18
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18
2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .19
2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . .38
3.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . .38
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .39
3.3 Estimated Power Usage Calculations. . . . . . . . . . . . . .46
3.4 Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.5 DDR Memory System Guidelines . . . . . . . . . . . . . . . . .50
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
DDR DRAM Output Timing Diagram . . . . . . . . . . . . .
DDR DRAM AC Test Load . . . . . . . . . . . . . . . . . . . . .
TDM Receive Signals. . . . . . . . . . . . . . . . . . . . . . . . .
TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . .
Read Timing Diagram, Single Data Strobe . . . . . . . .
Read Timing Diagram, Double Data Strobe . . . . . . . .
Write Timing Diagram, Single Data Strobe. . . . . . . . .
Write Timing Diagram, Double Data Strobe . . . . . . . .
Host DMA Read Timing Diagram, HPCR[OAD] = 0 . .
Host DMA Write Timing Diagram, HPCR[OAD] = 0 . .
I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .
UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . .
EE Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
EVNT Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GPI/GPO Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . .
Test Clock Input Timing Diagram . . . . . . . . . . . . . . . .
Boundary Scan (JTAG) Timing Diagram . . . . . . . . . .
Test Access Port Timing Diagram . . . . . . . . . . . . . . .
TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Sequencing Case 1 . . . . . . . . . . . . . . . . . . . .
Voltage Sequencing Case 2 . . . . . . . . . . . . . . . . . . . .
Voltage Sequencing Case 3 . . . . . . . . . . . . . . . . . . . .
Voltage Sequencing Case 4 . . . . . . . . . . . . . . . . . . . .
Voltage Sequencing Case 5 . . . . . . . . . . . . . . . . . . . .
PLL Power Supply Filter Circuits . . . . . . . . . . . . . . . .
SSTL Termination Techniques . . . . . . . . . . . . . . . . . .
SSTL Power Value . . . . . . . . . . . . . . . . . . . . . . . . . . .
26
26
27
27
29
30
30
31
31
32
33
34
34
34
35
35
36
37
37
37
40
41
42
43
44
45
50
51
3
4
5
6
7
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
MSC7110 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 3
MSC7110 Molded Array Process-Ball Grid Array
(MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4
MSC7110 Molded Array Process-Ball Grid Array
(MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5
Timing Diagram for a Reset Configuration Write . . . . 24
DDR DRAM Input Timing Diagram . . . . . . . . . . . . . . 24
MSC7110 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
2
Freescale Semiconductor
JTAG Port
DMA
(32 Channel)
JTAG
AMDMA
ASM2
64
128
to IPBus
SC1400
Core
OCE10
Boot ROM
(8 KB)
Trace
Buffer
(8 KB)
DSP
Extended
Core
ASEMI
64
from
IPBus
External
Memory
Interface
External Bus
32
Interrupt Control
Fetch
Unit
Instruction
Cache
(16 KB)
Extended
Core
Interface
AMIC
128
Interrupts
HDI16
Port
TDM
PLL/Clock
I
2
C
RS-232
GPIO
AHB-Lite Crossbar Switch
MUX
ASTH
64
Host
Interface
(HDI16)
32
1 TDM
APB Bridge
PLL/Clock
APB
AMEC
64
ASAPB
32
I
2
C
UART
GPIO
System Ctrl
64
64
64
ASIB
32
IB Bridge
128
M1
SRAM
(64 KB)
ASM1
P XA XB
32
Watchdog
Event Port
BTMs
Events
to EMI
to DMA
Note: The arrows show the
direction of the transfer.
to/from OCE10
Timers
IPBus
Figure 1. MSC7110 Block Diagram
MSC7110 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
3
Pin Assignments
1
1.1
Pin Assignments
MAP-BGA Ball Layout Diagrams
Top View
1
2
GND
This section includes diagrams of the MSC7110 package ball grid array layouts and pinout allocation tables.
Top and bottom views of the MAP-BGA package are shown in
Figure 2
and
Figure 3
with their ball location index numbers.
3
DQM1
4
DQS2
5
CK
6
CK
7
HD15
8
HD12
9
HD10
10
HD7
11
HD6
12
HD4
13
HD1
14
HD0
15
GND
16
NC
17
NC
18
NC
19
NC
20
NC
A
GND
B
V
DDM
NC
CS0
DQM2
DQS3
DQS0
CKE
WE
HD14
HD11
HD8
HD5
HD2
NC
NC
NC
NC
NC
NC
NC
C
D24
D30
D25
CS1
DQM3
DQM0
DQS1
RAS
CAS
HD13
HD9
HD3
NC
NC
NC
NC
NC
NC
NC
NC
D
V
DDM
D28
D27
GND
V
DDM
V
DDM
V
DDM
V
DDM
V
DDM
V
DDM
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDC
NC
NC
NC
E
GND
D26
D31
V
DDM
V
DDM
V
DDC
V
DDC
V
DDC
V
DDC
V
DDM
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDC
V
DDC
NC
NC
NC
F
V
DDM
D15
D29
V
DDC
V
DDC
V
DDC
GND
GND
GND
V
DDM
V
DDM
GND
GND
GND
V
DDIO
V
DDC
V
DDC
NC
NC
NC
G
GND
D13
GND
V
DDM
V
DDM
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
DDIO
V
DDIO
V
DDC
NC
NC
NC
H
D14
D12
D11
V
DDM
V
DDM
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
DDIO
V
DDIO
V
DDC
NC
HA2
HA1
J
D10
V
DDM
D9
V
DDM
V
DDM
V
DDM
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
DDIO
V
DDC
HA3
HACK
HREQ
K
D0
GND
D8
V
DDC
V
DDM
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
DDIO
V
DDIO
V
DDC
HA0
HDDS
HDS
L
D1
GND
D3
V
DDC
V
DDM
GND
GND
GND
GND
GND
GND
GND
GND
V
DDIO
V
DDIO
V
DDIO
V
DDC
HCS2
HCS1
HRW
M
D2
V
DDM
D5
V
DDM
V
DDM
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
DDC
V
DDC
SDA
UTXD
URXD
N
D4
D6
V
REF
V
DDM
V
DDM
V
DDM
GND
GND
GND
GND
GND
GND
GND
GND
V
DDIO
V
DDC
V
DDC
CLKIN
SCL
V
SSPLL
P
D7
D17
D16
V
DDM
V
DDM
V
DDM
GND
GND
GND
GND
GND
GND
GND
GND
V
DDIO
V
DDIO
V
DDC
PORESET
TPSEL V
DDPLL
R
GND
D19
D18
V
DDM
V
DDM
V
DDM
GND
V
DDM
GND
V
DDM
GND
GND
V
DDIO
GND
V
DDIO
V
DDIO
V
DDC
TDO
EE0
TEST0
T
V
DDM
D20
D22
V
DDM
V
DDM
V
DDC
V
DDM
V
DDM
V
DDC
V
DDM
V
DDM
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDC
V
DDC
NC
TMS
HRESET
U
GND
D21
D23
V
DDM
V
DDC
V
DDC
V
DDC
V
DDC
V
DDC
V
DDC
V
DDC
V
DDC
V
DDC
V
DDC
V
DDC
V
DDC
V
DDC
NC
TCK
TRST
V
V
DDM
NC
A13
A11
A10
A5
A2
BA0
NC
EVNT0 EVNT4 T0TCK
GPIA4
GPIA0 GPIA28 GPID6 GPIA22 GPIA24
NC
TDI
W
GND
V
DDM
A12
A8
A7
A6
A3
NC
EVNT1 EVNT2 T0RFS T0TFS
GPIA3
GPIA1 GDPD4 GPIA27 GPIA19 GPIA23 GPIA26 H8BIT
Y
V
DDM
GND
A9
A1
A0
A4
BA1
NMI
EVNT3 T0RCK
T0RD
TOTD
GPIA5
GPIA2 GPIA29 GPID5 GPIA20 GPIA21
GND
GPIA25
Note:
The display is for mask set 1L44X. For mask set 1M88B, A16 is BM3 and B15 is BM2.
Figure 2. MSC7110 Molded Array Process-Ball Grid Array (MAP-BGA), Top View
MSC7110 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
4
Freescale Semiconductor
Pin Assignments
Bottom View
20
A
NC
19
NC
18
NC
17
NC
16
NC
15
GND
14
HD0
13
HD1
12
HD4
11
HD6
10
HD7
9
HD10
8
HD12
7
HD15
6
CK
5
CK
4
DQS2
3
DQM1
2
GND
1
GND
B
NC
NC
NC
NC
NC
NC
NC
HD2
HD5
HD8
HD11
HD14
WE
CKE
DQS0
DQS3
DQM2
CS0
NC
V
DDM
C
NC
NC
NC
NC
NC
NC
NC
NC
HD3
HD9
HD13
CAS
RAS
DQS1
DQM0
DQM3
CS1
D25
D30
D24
D
NC
NC
NC
V
DD
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDM
V
DDM
V
DDM
V
DDM
V
DDM
V
DDM
GND
D27
D28
V
DDM
E
NC
NC
NC
V
DD
V
DD
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDM
V
DD
V
DD
V
DD
V
DD
V
DDM
V
DDM
D31
D26
GND
F
NC
NC
NC
V
DD
V
DD
V
DDIO
GND
GND
GND
V
DDM
V
DDM
GND
GND
GND
V
DD
V
DD
V
DD
D29
D15
V
DDM
G
NC
NC
NC
V
DD
V
DDIO
V
DDIO
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
DDM
V
DDM
GND
D13
GND
H
HA1
HA2
NC
V
DD
V
DDIO
V
DDIO
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
DDM
V
DDM
D11
D12
D14
J
HREQ
HACK
HA3
V
DD
V
DDIO
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
DDM
V
DDM
V
DDM
D9
V
DDM
D10
K
HDS
HDDS
HA0
V
DD
V
DDIO
V
DDIO
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
DDM
V
DD
D8
GND
D0
L
HRW
HCS1
HCS2
V
DD
V
DDIO
V
DDIO
V
DDIO
GND
GND
GND
GND
GND
GND
GND
GND
V
DDM
V
DD
D3
GND
D1
M
URXD
UTXD
SDA
V
DD
V
DD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
DDM
V
DDM
D5
V
DDM
D2
N
V
SSPLL
SCL
CLKIN
V
DD
V
DD
V
DDIO
GND
GND
GND
GND
GND
GND
GND
GND
V
DDM
V
DDM
V
DDM
V
REF
D6
D4
P
V
DDPLL
TPSEL
PORESET
V
DD
V
DDIO
V
DDIO
GND
GND
GND
GND
GND
GND
GND
GND
V
DDM
V
DDM
V
DDM
D16
D17
D7
R
TEST0
EE0
TDO
V
DD
V
DDIO
V
DDIO
GND
V
DDIO
GND
GND
V
DDM
GND
V
DDM
GND
V
DDM
V
DDM
V
DDM
D18
D19
GND
T
HRESET
TMS
NC
V
DD
V
DD
V
DDIO
V
DDIO
V
DDIO
V
DDIO
V
DDM
V
DDM
V
DD
V
DDM
V
DDM
V
DD
V
DDM
V
DDM
D22
D20
V
DDM
U
TRST
TCK
NC
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DDM
D23
D21
GND
V
TDI
NC
GPIA24 GPIA22 GPID6 GPIA28 GPIA0
GPIA4
T0TCK EVNT4 EVNT0
NC
BA0
A2
A5
A10
A11
A13
NC
V
DDM
W
H8BIT GPIA26 GPIA23 GPIA19 GPIA27 GDPD4 GPIA1
GPIA3
T0TFS T0RFS EVNT2 EVNT1
NC
A3
A6
A7
A8
A12
V
DDM
GND
Y
GPIA25
GND
GPIA21 GPIA20 GPID5 GPIA29 GPIA2
GPIA5
TOTD
T0RD
T0RCK EVNT3
NMI
BA1
A4
A0
A1
A9
GND
V
DDM
Note:
The display is for mask set 1L44X. For mask set 1M88B, A16 is BM3 and B15 is BM2.
Figure 3. MSC7110 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View
MSC7110 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
5
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