MC68376BGVAB20 datasheet, PDF - EEWORLD Datasheet

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MC68376BGVAB20: DescriptionIC MCU 32BIT ROMLESS 160QFP; Categorysemiconductor The embedded processor and controller; File Size7MB，434 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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MC68376BGVAB20 Overview

IC MCU 32BIT ROMLESS 160QFP

MC68376BGVAB20 Parametric

Parameter Name	Attribute value
core processor	CPU32
core size	32-bit
speed	20MHz
Connectivity	CANbus，EBI/EMI，SCI，SPI
Peripheral	POR，PWM，WDT
Number of I/Os	18
Program storage capacity	-
Program memory type	ROMless
EEPROM capacity	-
RAM capacity	7.5K x 8
Voltage - Power Supply (Vcc/Vdd)	4.75 V ~ 5.25 V
data converter	A/D 16x10b
Oscillator type	external
Operating temperature	-40°C ~ 105°C（TA）
Package/casing	160-BQFP
Supplier device packaging	160-QFP（28x28）

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MC68336/376

USER’S MANUAL

TouCAN is a trademark of Motorola, Inc.

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability

of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and

all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including

"Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others.

Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to

support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer

purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries,

affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal

injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.

MOTOROLA and

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

TABLE OF CONTENTS

Paragraph

Title

SECTION 1 INTRODUCTION

SECTION 2 NOMENCLATURE

2.1

2.2

2.3

2.4

2.5

Symbols and Operators ............................................................................. 2-1

CPU32 Registers ....................................................................................... 2-2

Pin and Signal Mnemonics ........................................................................ 2-2

Conventions .............................................................................................. 2-8

SECTION 3 OVERVIEW

3.1

3.1.1

3.1.2

3.1.3

3.1.4

3.1.5

3.1.6

3.1.7

3.1.8

3.1.9

3.1.10

3.2

3.3

3.4

3.5

3.6

3.7

MCU Features ........................................................................................... 3-1

Central Processing Unit (CPU32) ...................................................... 3-1

System Integration Module (SIM) ...................................................... 3-1

Standby RAM Module (SRAM) .......................................................... 3-1

Masked ROM Module (MRM) ............................................................ 3-1

10-Bit Queued Analog-to-Digital Converter (QADC) ......................... 3-2

Queued Serial Module (QSM) ........................................................... 3-2

Configurable Timer Module Version 4 (CTM4) .................................. 3-2

Time Processor Unit (TPU) ............................................................... 3-2

Static RAM Module with TPU Emulation Capability (TPURAM) ........ 3-2

CAN 2.0B Controller Module (TouCAN) ............................................ 3-3

Intermodule Bus ........................................................................................ 3-3

System Block Diagram and Pin Assignment Diagrams ............................. 3-3

Pin Descriptions ........................................................................................ 3-6

Signal Descriptions .................................................................................... 3-9

Internal Register Map .............................................................................. 3-13

Address Space Maps .............................................................................. 3-14

SECTION 4 CENTRAL PROCESSOR UNIT

4.1

General ...................................................................................................... 4-1

4.2

CPU32 Registers ....................................................................................... 4-2

4.2.1

Data Registers ................................................................................... 4-4

4.2.2

Address Registers ............................................................................. 4-5

4.2.3

Program Counter ............................................................................... 4-6

4.2.4

Control Registers ............................................................................... 4-6

4.2.4.1

Status Register .......................................................................... 4-6

4.2.4.2

Alternate Function Code Registers ........................................... 4-7

4.2.5

Vector Base Register (VBR) .............................................................. 4-7

4.3

Memory Organization ................................................................................ 4-7

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Page

TABLE OF CONTENTS

Paragraph

(Continued)

Title

Page

4.4

Virtual Memory .......................................................................................... 4-9

4.5

Addressing Modes ..................................................................................... 4-9

4.6

Processing States ..................................................................................... 4-9

4.7

Privilege Levels ....................................................................................... 4-10

4.8

Instructions .............................................................................................. 4-10

4.8.1

M68000 Family Compatibility .......................................................... 4-14

4.8.2

Special Control Instructions ............................................................. 4-14

4.8.2.1

Low-Power Stop (LPSTOP) .................................................... 4-14

4.8.2.2

Table Lookup and Interpolate (TBL) ....................................... 4-14

4.8.2.3

Loop Mode Instruction Execution ............................................ 4-15

4.9

Exception Processing .............................................................................. 4-15

4.9.1

Exception Vectors ........................................................................... 4-15

4.9.2

Types of Exceptions ........................................................................ 4-17

4.9.3

Exception Processing Sequence ..................................................... 4-17

4.10

Development Support .............................................................................. 4-17

4.10.1

M68000 Family Development Support ............................................ 4-18

4.10.2

Background Debug Mode ................................................................ 4-18

4.10.3

Enabling BDM ................................................................................. 4-19

4.10.4

BDM Sources .................................................................................. 4-19

4.10.4.1

External BKPT Signal .............................................................. 4-20

4.10.4.2

BGND Instruction .................................................................... 4-20

4.10.4.3

Double Bus Fault ..................................................................... 4-20

4.10.4.4

Peripheral Breakpoints ............................................................ 4-20

4.10.5

Entering BDM .................................................................................. 4-20

4.10.6

BDM Commands ............................................................................. 4-21

4.10.7

Background Mode Registers ........................................................... 4-22

4.10.7.1

Fault Address Register (FAR) ................................................. 4-22

4.10.7.2

Return Program Counter (RPC) .............................................. 4-22

4.10.7.3

Current Instruction Program Counter (PCC) ........................... 4-23

4.10.8

Returning from BDM ........................................................................ 4-23

4.10.9

Serial Interface ................................................................................ 4-23

4.10.10

Recommended BDM Connection .................................................... 4-25

4.10.11

Deterministic Opcode Tracking ....................................................... 4-26

4.10.12

On-Chip Breakpoint Hardware ........................................................ 4-26

SECTION 5 SYSTEM INTEGRATION MODULE

5.1

5.2

5.2.1

5.2.2

5.2.3

General ...................................................................................................... 5-1

System Configuration ................................................................................ 5-2

Module Mapping ................................................................................ 5-2

Interrupt Arbitration ............................................................................ 5-2

Show Internal Cycles ......................................................................... 5-3

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TABLE OF CONTENTS

Paragraph

(Continued)

Title

Page

5.2.4

5.2.5

Freeze Operation .............................................................................. 5-3

5.3

System Clock ............................................................................................ 5-4

5.3.1

Clock Sources ................................................................................... 5-4

5.3.2

Clock Synthesizer Operation ............................................................. 5-5

5.3.3

External Bus Clock .......................................................................... 5-12

5.3.4

Low-Power Operation ...................................................................... 5-12

5.4

System Protection ................................................................................... 5-14

5.4.1

Reset Status .................................................................................... 5-14

5.4.2

Bus Monitor ..................................................................................... 5-14

5.4.3

Halt Monitor ..................................................................................... 5-15

5.4.4

Spurious Interrupt Monitor ............................................................... 5-15

5.4.5

Software Watchdog ......................................................................... 5-15

5.4.6

Periodic Interrupt Timer ................................................................... 5-17

5.4.7

Interrupt Priority and Vectoring ........................................................ 5-18

5.4.8

Low-Power STOP Mode Operation ................................................. 5-19

5.5

External Bus Interface ............................................................................. 5-19

5.5.1

Bus Control Signals ......................................................................... 5-21

5.5.1.1

Address Bus ............................................................................ 5-21

5.5.1.2

Address Strobe ....................................................................... 5-21

5.5.1.3

Data Bus ................................................................................. 5-21

5.5.1.4

Data Strobe ............................................................................. 5-22

5.5.1.5

Read/Write Signal ................................................................... 5-22

5.5.1.6

Size Signals ............................................................................ 5-22

5.5.1.7

Function Codes ....................................................................... 5-22

5.5.1.8

Data and Size Acknowledge Signals ...................................... 5-23

5.5.1.9

Bus Error Signal ...................................................................... 5-23

5.5.1.10

Halt Signal ............................................................................... 5-23

5.5.1.11

Autovector Signal .................................................................... 5-24

5.5.2

Dynamic Bus Sizing ........................................................................ 5-24

5.5.3

Operand Alignment ......................................................................... 5-25

5.5.4

Misaligned Operands ...................................................................... 5-25

5.5.5

Operand Transfer Cases ................................................................. 5-26

5.6

Bus Operation ......................................................................................... 5-26

5.6.1

Synchronization to CLKOUT ........................................................... 5-26

5.6.2

Regular Bus Cycles ......................................................................... 5-27

5.6.2.1

Read Cycle .............................................................................. 5-28

5.6.2.2

Write Cycle .............................................................................. 5-29

5.6.3

Fast Termination Cycles .................................................................. 5-30

5.6.4

CPU Space Cycles .......................................................................... 5-30

5.6.4.1

Breakpoint Acknowledge Cycle ............................................... 5-31

MC68336/376

USER’S MANUAL

MOTOROLA

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