MSC7115VF1000 datasheet, PDF - EEWORLD Datasheet

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MSC7115VF1000: DescriptionDSP 16BIT W/DDR CTRLR 400-MAPBGA; CategoryThe embedded processor and controller Microcontrollers and processors; File Size905KB，56 Pages; ManufacturerNXP; Websitehttps://www.nxp.com

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MSC7115VF1000 Overview

DSP 16BIT W/DDR CTRLR 400-MAPBGA

MSC7115VF1000 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	NXP
Parts packaging code	BGA
package instruction	17 X 17 MM, BGA-400
Contacts	400
Reach Compliance Code	not_compliant
ECCN code	3A001.A.3
Address bus width	14
barrel shifter	NO
bit size	16
boundary scan	YES
maximum clock frequency	266 MHz
External data bus width	32
Format	FIXED POINT
Internal bus architecture	MULTIPLE
JESD-30 code	S-PBGA-B400
JESD-609 code	e0
length	17 mm
low power mode	YES
Humidity sensitivity level	3
Number of terminals	400
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LFBGA
Encapsulate equivalent code	BGA400,20X20,32
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH
power supply	1.2,2.5,3.3 V
Certification status	Not Qualified
RAM (number of words)	196608
Maximum seat height	1.6 mm
Maximum supply voltage	1.26 V
Minimum supply voltage	1.14 V
Nominal supply voltage	1.2 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Lead/Silver (Sn/Pb/Ag)
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	17 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches	1

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Freescale Semiconductor

Data Sheet

Document Number: MSC7115

Rev. 11, 4/2008

MSC7115

Low-Cost 16-bit DSP with

DDR Controller

MAP-BGA–400

17 mm

• StarCore

SC1400 DSP extended core with one SC1400 DSP

core, 192 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte

instruction cache (ICache), four-entry write buffer, programmable

interrupt controller (PIC), and low-power Wait and Stop

processing modes.

• 192 Kbyte M2 memory for critical data and temporary data

buffering.

• 8 Kbyte boot ROM.

• AHB-Lite crossbar switch that allows parallel data transfers

between four master ports and six slave ports, where each port

connects to an AHB-Lite bus; fixed or round robin priority

programmable at each slave port; programmable bus parking at

each slave port; low power mode.

• Internal PLL generates up to 266 MHz clock for the SC1400 core

and up to 133 MHz for the crossbar switch, DMA channels, M2

memory, and other peripherals.

• Clock synthesis module provides predivision of PLL input clock;

independent clocking of the internal timers and DDR module;

programmable operation in the SC1400 low power Stop mode;

independent shutdown of different regions of the device.

• Enhanced 16-bit wide host interface (HDI16) provides a glueless

connection to industry-standard microcomputers,

microprocessors, and DSPs and can also operate with an 8-bit host

data bus, making if fully compatible with the DSP56300 HI08

from the external host side.

• DDR memory controller that supports byte enables for up to a

32-bit data bus; glueless interface to 133 MHz 14-bit page mode

DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;

and 16-bit or 32-bit external data bus.

• Programmable memory interface with independent read buffers,

programmable predictive read feature for each buffer, and a write

buffer.

• System control unit performs software watchdog timer function;

includes programmable bus time-out monitors on AHB-Lite slave

buses; includes bus error detection and programmable time-out

monitors on AHB-Lite master buses; and has address

out-of-range detection on each crossbar switch buses.

• Event port collects and counts important signal events including

DMA and interrupt requests and trigger events such as interrupts,

breakpoints, DMA transfers, or wake-up events; units operate

independently, in sequence, or triggered externally; can be used

standalone or with the OCE10.

• Multi-channel DMA controller with 32 time-multiplexed

unidirectional channels, priority-based time-multiplexing

between channels using 32 internal priority levels, fixed- or

round-robin-priority operation, major-minor loop structure, and

DONE or DRACK protocol from requesting units.

• Two independent TDM modules with independent receive and

transmit, programmable sharing of frame sync and clock,

programmable word size (8 or 16-bit), hardware-base

A-law/μ-law conversion, up to 50 Mbps data rate per TDM, up to

128 channels, with glueless interface to E1/T1 frames and MVIP,

SCAS, and H.110 buses.

• UART with full-duplex operation up to 5.0 Mbps.

• Up to 41 general-purpose input/output (GPIO) ports.

• I

C interface that allows booting from EEPROM devices up to 1

Mbyte.

• Two quad timer modules, each with sixteen configurable 16-bit

timers.

• fieldBIST™ unit detects and provides visibility into unlikely field

failures for systems with high availability to ensure structural

integrity, that the device operates at the rated speed, is free from

reliability defects, and reports diagnostics for partial or complete

device inoperability.

• Standard JTAG interface allows easy integration to system

firmware and internal on-chip emulation (OCE10) module.

• Optional booting external host via 8-bit or 16-bit access through

the HDI16, I

C, or SPI using in the boot ROM to access serial SPI

Flash/EEPROM devices; different clocking options during boot

with the PLL on or off using a variety of input frequency ranges.

MSC7115VF1000 Related Products

	MSC7115VF1000	MSC7115VM800	MSC7115VM1000
Description	DSP 16BIT W/DDR CTRLR 400-MAPBGA	IC DSP PROCESSOR 16BIT 400MAPBGA	DSP 16BIT W/DDR CTRLR 400-MAPBGA
Is it Rohs certified?	incompatible	conform to	conform to
Maker	NXP	NXP	NXP
Parts packaging code	BGA	BGA	BGA
package instruction	17 X 17 MM, BGA-400	17 X 17 MM, LEAD FREE, BGA-400	17 X 17 MM, LEAD FREE, BGA-400
Contacts	400	400	400
Reach Compliance Code	not_compliant	unknown	unknown
ECCN code	3A001.A.3	3A001.A.3	3A001.A.3
Address bus width	14	14	14
barrel shifter	NO	NO	NO
bit size	16	16	16
boundary scan	YES	YES	YES
maximum clock frequency	266 MHz	200 MHz	266 MHz
External data bus width	32	32	32
Format	FIXED POINT	FIXED POINT	FIXED POINT
Internal bus architecture	MULTIPLE	MULTIPLE	MULTIPLE
JESD-30 code	S-PBGA-B400	S-PBGA-B400	S-PBGA-B400
length	17 mm	17 mm	17 mm
low power mode	YES	YES	YES
Humidity sensitivity level	3	3	3
Number of terminals	400	400	400
Minimum operating temperature	-40 °C	-40 °C	-40 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LFBGA	LFBGA	LFBGA
Encapsulate equivalent code	BGA400,20X20,32	BGA400,20X20,32	BGA400,20X20,32
Package shape	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH	GRID ARRAY, LOW PROFILE, FINE PITCH
power supply	1.2,2.5,3.3 V	1.2,2.5,3.3 V	1.2,2.5,3.3 V
Certification status	Not Qualified	Not Qualified	Not Qualified
RAM (number of words)	196608	196608	196608
Maximum seat height	1.6 mm	1.6 mm	1.6 mm
Maximum supply voltage	1.26 V	1.26 V	1.26 V
Minimum supply voltage	1.14 V	1.14 V	1.14 V
Nominal supply voltage	1.2 V	1.2 V	1.2 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Terminal surface	Tin/Lead/Silver (Sn/Pb/Ag)	Tin/Silver/Copper - with Nickel barrier	Tin/Silver/Copper - with Nickel barrier
Terminal form	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM
width	17 mm	17 mm	17 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER
Base Number Matches	1	1	1

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