a
FEATURES
Throughput: 100 kSPS
INL: 3 LSB Max ( 0.0046% of Full-Scale)
16-Bit Resolution with No Missing Codes
S/(N+D): 87 dB Min @ 10 kHz, 90 dB Typ @ 45 kHz
THD: –96 dB Max @ 10 kHz
Analog Input Voltage Range: 0 V to 2.5 V
Both AC and DC Specifications
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface
/DSP Compatible
SPI
®
/QSPI™/MICROWIRE™
Single 5 V Supply Operation
21 mW Typical Power Dissipation, 21 W @ 100 SPS
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flatpack (LQFP)
48-Lead Chip Scale Package (LFCSP)
Pin-to-Pin Compatible with the AD7664
APPLICATIONS
Data Acquisition
Battery-Powered Systems
PCMCIA
Instrumentation
Automatic Test Equipment
Scanners
Medical Instruments
Process Control
IN
INGND
16-Bit, 100 kSPS PulSAR
Unipolar CMOS ADC
AD7660
®
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND REF REFGND
DVDD
DGND
OVDD
SERIAL
PORT
SWITCHED
CAP DAC
16
D[15:0]
BUSY
PARALLEL
INTERFACE
PD
RESET
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
RD
CS
SER/PAR
OB/2C
OGND
AD7660
CNVST
Table I. PulSAR Selection
Type/kSPS
Pseudo
Differential
True Bipolar
True
Differential
18-Bit
100–250
500–570
800–1000
AD7651
AD7650/AD7652 AD7653
AD7660/AD7661 AD7664/AD7666 AD7667
AD7663
AD7675
AD7678
AD7665
AD7676
AD7679
AD7654
AD7655
AD7671
AD7677
AD7674
GENERAL DESCRIPTION
The AD7660 is a 16-bit, 100 kSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V power
supply. The part contains an internal conversion clock, error cor-
rection circuits, and both serial and parallel system interface ports.
The AD7660 is hardware factory-calibrated and is comprehen-
sively tested to ensure ac parameters such as signal-to-noise ratio
(SNR) and total harmonic distortion (THD), in addition to the
more traditional dc parameters of gain, offset, and linearity.
It is fabricated using Analog Devices’ high performance,
0.6 micron CMOS process with correspondingly low cost and is
available in a 48-lead LQFP and a tiny 48-lead LFCSP with
operation specified from –40∞C to +85∞C.
Simultaneous/
Multichannel
PRODUCT HIGHLIGHTS
1. Fast Throughput
The AD7660 is a 100 kSPS, charge redistribution, 16-bit
SAR ADC with internal error correction circuitry.
2. Superior INL
The AD7660 has a maximum integral nonlinearity of 3 LSBs
with no missing 16-bit code.
3. Single-Supply Operation
The AD7660 operates from a single 5 V supply and only
dissipates 21 mW typical. Its power dissipation decreases
with the throughput to, for instance, only 21
mW
at a 100 SPS
throughput. It consumes 7
mW
maximum when in power-down.
4. Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement com-
patible with both 3 V or 5 V logic.
REV.
E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
www.analog.com
Fax:781/326-8703
© 2001-2016 Analog Devices, Inc. All rights reserved.
AD7660–SPECIFICATIONS
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
RESOLUTION
ANALOG INPUT
Voltage Range
Operating Input Voltage
Analog Input CMRR
Input Current
Input Impedance
THROUGHPUT SPEED
Complete Cycle
Throughput Rate
DC ACCURACY
Integral Linearity Error
Differential Linearity Error
No Missing Codes
Transition Noise
2
Full-Scale Error
3
Unipolar Zero Error
3
Power Supply Sensitivity
AC ACCURACY
Signal-to-Noise
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise+Distortion)
V
IN
– V
INGND
V
IN
V
INGND
f
IN
= 25 kHz
100 kSPS Throughput
Conditions
Min
16
0
–0.1
–0.1
70
325
See Analog Input Section
10
100
+3
+1.75
0.75
±
0.045
±
1
±
3
87
96
100
–96
–100
87
90
30
820
2
5
Full-Scale Step
2.3
100 kSPS Throughput
2.5
22
8
AVDD – 1.85
90
90
±
0.08
±
5
V
REF
+3
+0.5
Typ
Max
Unit
Bits
V
V
V
dB
nA
0
–3
–1
16
REF = 2.5 V
AVDD = 5 V
±
5%
f
IN
= 10 kHz
f
IN
= 45 kHz
f
IN
= 10 kHz
f
IN
= 45 kHz
f
IN
= 10 kHz
f
IN
= 45 kHz
f
IN
= 10 kHz
f
IN
= 45 kHz
–60 dB Input
ms
kSPS
LSB
1
LSB
Bits
LSB
% of FSR
LSB
LSB
dB
4
dB
dB
dB
dB
dB
dB
dB
dB
kHz
ns
ps rms
ms
V
mA
–3 dB Input Bandwidth
SAMPLING DYNAMICS
Aperture Delay
Aperture Jitter
Transient Response
REFERENCE
External Reference Voltage Range
External Reference Current Drain
POWER SUPPLIES
Specified Performance
AVDD
DVDD
OVDD
Operating Current
AVDD
DVDD
5
OVDD
5
Power Dissipation
5
4.75
4.75
2.7
100 kSPS Throughput
5
5
5.25
5.25
5.25
V
V
V
mA
mA
mA
mW
mW
mW
100 kSPS Throughput
100 SPS Throughput
in Power-Down Mode
5, 6
3.2
1
10
21
21
25
7
DIGITAL INPUTS
Logic Levels
V
IL
V
IH
I
IL
I
IH
DIGITAL OUTPUTS
Data Format
Pipeline Delay
V
OL
V
OH
I
SINK
= 1.6 mA
I
SOURCE
= –500
mA
–0.3
+2.0
–1
–1
+0.8
OVDD + 0.3
+1
+1
V
V
mA
mA
Parallel or Serial 16-Bit
Conversion Results Available Immediately
after Completed Conversion
0.4
OVDD – 0.6
V
V
–2–
REV.
E
AD7660
Parameter
TEMPERATURE RANGE
Specified Performance
Conditions
T
MIN
to T
MAX
Min
–40
Typ
Max
+85
Unit
∞C
NOTES
1
LSB means least significant bit. With the 0 V to 2.5 V input range, one LSB is 38.15
mV.
2
Typical rms noise at worst-case transitions and temperatures.
3
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
4
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
5
Tested in Parallel Reading Mode.
6
With all digital inputs forced to DVDD or DGND respectively.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
(–40 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Parameter
REFER TO FIGURES 11 AND 12
Convert Pulsewidth
Time between Conversions
CNVST
LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Master Serial Read after Convert Mode
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth
REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)
CNVST
LOW to DATA Valid Delay
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
REFER TO FIGURE 16 AND 17 (Master Serial Interface Modes)
1
CS
LOW to SYNC Valid Delay
CS
LOW to Internal SCLK Valid Delay
CS
LOW to SDOUT Delay
CNVST
LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
Internal SCLK HIGH (INVSCLK Low)
2
Internal SCLK LOW (INVSCLK Low)
2
SDOUT Valid Setup Time
SDOUT Valid Hold Time
SCLK Last Edge to SYNC Delay
CS
HIGH to SYNC HI-Z
CS
HIGH to Internal SCLK HI-Z
CS
HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
CNVST
LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
REFER TO FIGURES 18 AND 20 (Slave Serial Interface Modes)
1
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
Symbol
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
t
30
t
31
t
32
t
33
t
34
t
35
t
36
t
37
Min
5
10
15
2
2
10
2
8
10
2
45
5
40
15
10
10
10
500
4
40
30
9.5
4.5
3
3
75
Typ
Max
Unit
ns
ms
ns
ms
ns
ns
ms
ms
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
10
10
10
3.2
1.5
50
5
3
5
5
25
10
10
16
NOTES
1
In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C
L
of 10 pF; otherwise, the load is 60 pF maximum.
2
If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.
Specifications subject to change without notice.
REV.
E
–3–
AD7660
ABSOLUTE MAXIMUM RATINGS
1
PIN CONFIGURATION
NC
NC
NC
NC
NC
IN
NC
NC
NC
INGND
REFGND
REF
AGND
1
AVDD
2
NC
3
DGND
4
OB/2C
5
NC
6
NC
7
SER/PAR
8
D0
9
D1
10
D2
11
D3
12
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
See Analog Input section.
3
Specification is for device in free air: 48-Lead LQFP:
q
JA
= 91∞C/W,
q
JC
= 30∞C/W.
4
Specification is for device in free air: 48-Lead LFCSP:
q
JA
= 26∞C/W.
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EPAD IS CONNECTED TO GROUND; HOWEVER,
THIS CONNECTION IS NOT REQUIRED TO MEET
SPECIFIED PERFORMANCE.
1.6mA
I
OL
TO OUTPUT
PIN
1.4V
C
L
60pF
*
500 A
I
OH
2V
0.8V
*IN
SERIAL INTERFACE MODES, THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
C
L
OF 10pF; OTHERWISE, THE LOAD IS 60pF MAXIMUM.
t
DELAY
2V
0.8V
Figure 1. Load Circuit for Digital Interface Timing
Figure 2. Voltage Reference Levels for Timings
ORDERING GUIDE
Model
1
AD7660ASTZ
AD7660ASTZRL
AD7660ACPZRL
NOTES
1
Z
Temperature Range
–40∞C to +85∞C
–40∞C to +85∞C
–40∞C to +85∞C
Package Description
48-Lead LQFP
48-Lead LQFP
48-Lead LFCSP
= RoHS Compliant Part.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD7660 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
D4/EXT/INT
D5/INVSYNC
D6/INVSCLK
D7/RDC/SDIN
OGND
OVDD
DVDD
DGND
D8/SDOUT
D9/SCLK
D10/SYNC
D11/RDERROR
Analog Inputs
IN
2
, REF, INGND, REFGND . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . AVDD + 0.3 V to AGND – 0.3 V
Ground Voltage Differences
AGND, DGND, OGND . . . . . . . . . . . . . . . . . . . . .
±
0.3 V
Supply Voltages
AVDD, DVDD, OVDD . . . . . . . . . . . . . . . . –0.3 V to +7 V
AVDD to DVDD, AVDD to OVDD . . . . . . . . . . . . .
±
7 V
DVDD to OVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
7 V
Digital Inputs
Except the Databus D(7:4) . . . –0.3 V to DVDD + 0.3 V
Databus Inputs D(7:4) . . . . . . –0.3 V to OVDD + 0.3 V
Internal Power Dissipation
3
. . . . . . . . . . . . . . . . . . . 700 mW
Internal Power Dissipation
4
. . . . . . . . . . . . . . . . . . . . . 2.5 W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range
(Soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300∞C
48
47
46
45
44
43
42
41
40
39
38
37
AD7660
TOP VIEW
(Not to Scale)
36
35
34
33
32
31
30
29
28
27
26
25
AGND
CNVST
PD
RESET
CS
RD
DGND
BUSY
D15
D14
D13
D12
13
14
15
16
17
18
19
20
21
22
23
24
t
DELAY
2V
0.8V
Package Option
ST-48
ST-48
CP-48-4
WARNING!
ESD SENSITIVE DEVICE
–4–
REV.
E
AD7660
PIN FUNCTION DESCRIPTIONS
Pin
No.
1
2
3, 6, 7,
40–42,
44–48
4
5
Mnemonic
AGND
AVDD
NC
Type
P
P
Description
Analog Power Ground Pin
Input Analog Power Pins. Nominally 5 V.
No Connect
DGND
OB/2C
DI
DI
8
9–12
13
SER/PAR
D[0:3]
D4
or EXT/INT
DI
DO
DI/O
14
D5
or INVSYNC
D6
or INVSCLK
D7
or RDC/SDIN
DI/O
15
DI/O
16
DI/O
17
18
19
20
21
OGND
OVDD
DVDD
DGND
D8
or SDOUT
P
P
P
P
DO
Must Be Tied to Digital Ground
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output is
straight binary; when LOW, the MSB is inverted resulting in a twos complement output from
its internal shift register.
Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH, the
Serial Interface Mode is selected and some bits of the DATA bus are used as a Serial Port.
Bit 0 to Bit 3 of the Parallel Port Data Output Bus. These pins are always outputs regardless
of the state of SER/PAR.
When SER/PAR is LOW, this output is used as the Bit 4 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital select input
for choosing the internal or an external data clock. With EXT/INT tied LOW, the internal
clock is selected on the SCLK output. With EXT/INT set to a logic HIGH, output data is
synchronized to an external clock signal connected to the SCLK input.
When SER/PAR is LOW, this output is used as the Bit 5 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the active state
of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH, SYNC is active LOW.
When SER/PAR is LOW, this output is used as the Bit 6 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the SCLK
signal. It is active in both Master and Slave Modes.
When SER/PAR is LOW, this output is used as the Bit 7 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this input, part of the Serial Port, is used as either an external data
input or a Read Mode selection input depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain the
conversion results from two or more ADCs onto a single SDOUT line. The digital data level
on SDIN is output on DATA with a delay of 16 SCLK periods after the initiation of the read
sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the Read Mode. When RDC/SDIN is
HIGH, the data is output on SDOUT during conversion. When RDC/SDIN is LOW, the
data is output on SDOUT only when the conversion is complete.
Input/Output Interface Digital Power Ground
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host
interface (5 V or 3 V).
Digital Power. Nominally at 5 V.
Digital Power Ground
When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this output, part of the Serial Port, is used as a serial data output
synchronized to SCLK. Conversion results are stored in an on-chip register. The AD7660
provides the conversion result, MSB first, from its internal shift register. The DATA format
is determined by the logic level of OB/2C. In Serial Mode, when EXT/INT is LOW, SDOUT
is valid on both edges of SCLK.
In Serial Mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next
falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next
rising edge.
REV.
E
–5–
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