PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840004
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
F
EATURES
• Four LVCMOS/LVTTL outputs, 15Ω typical output impedance
• Selectable crystal oscillator interface
or LVCMOS single-ended input
• Supports the following input frequencies: 212.5MHz,
159.375MHz, 156.25MHz, 106.25MHz and 53.125MHz
• VCO range: 470MHz - 750MHz
• RMS phase jitter @ 212.5MHz (637kHz - 10MHz):
0.98ps typical, V
DDO
= 3.3V
Phase noise:
Offset
Noise Power
100Hz ............... -88.8 dBc/Hz
1kHz ............. -109.0 dBc/Hz
10kHz ............. -116.1 dBc/Hz
100kkHz ............. -117.5 dBc/Hz
• Full 3.3V or 3.3V core/2.5V output supply mode
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
G
ENERAL
D
ESCRIPTION
The ICS840004 is a 4 output LVCMOS/LVTTL
Synthesizer optimized to generate Ethernet
HiPerClockS™
reference clock frequencies and is a member
of the HiPerClocks
TM
family of high perfor-
mance clock solutions from ICS. Using a
26.5625MHz, 18pF parallel resonant crystal, the following
frequencies can be generated based on the 2 frequency
select pins (F_SEL1:0): 212.5MHz, 159.375MHz,
156.25MHz, 106.25MHz, and 53.125MHz. The ICS840004
uses ICS’ 3
rd
generation low phase noise VCO technology
and can achieve 1ps or lower typical random rms phase
jitter, easily meeting Ethernet jitter requirements. The
ICS840004 is packaged in a small 20-pin TSSOP package.
IC
S
F
REQUENCY
S
ELECT
F
UNCTION
T
ABLE
Input
Frequency
26.5625
26.5625
26.5625
26.5625
26.04166
Inputs
M Divider
F_SEL1 F_SEL0
Value
0
0
24
0
1
1
0
1
0
1
1
24
24
24
24
N Divider
Value
3
4
6
12
4
M/N
Ratio Value
8
6
4
2
6
Output
Frequency
Range
212.5
159.375
106.25
53.125
156.25
B
LOCK
D
IAGRAM
OE
Pullup
F_SEL1:0 Pullup:Pullup
nPLL_SEL Pulldown
nXTAL_SEL
Pulldown
P
IN
A
SSIGNMENT
2
F_SEL0
nc
nXTAL_SEL
TEST_CLK
OE
MR
nPLL_SEL
V
DDA
nc
V
DD
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
F_SEL1
GND
Q0
Q1
V
DDO
Q2
Q3
GND
XTAL_IN
XTAL_OUT
XTAL_IN 26.5625MHz
OSC
XTAL_OUT
TEST_CLK Pulldown
0
F_SEL1:0
1
Phase
Detector
00
01
10
11
Q0
1
VCO
0
N
÷3
÷4
÷6
÷12
(default)
Q1
ICS840004
20-Lead TSSOP
6.5mm x 4.4mm x 0.92mm
package body
Q2
M = ÷24 (fixed)
Q3
G Package
Top View
MR
Pulldown
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840004AG
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 23, 2005
1
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840004
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
Type
Input
Pullup
Description
Frequency select pin. LVCMOS/LVTTL interface levels.
No connect.
Selects between the cr ystal or TEST_CLK inputs as the PLL reference
source. When HIGH, selects TEST_CLK. When LOW, selects XTAL
inpus. LVCMOS/LVTTL interface levels.
Single-ended LVCMOS/LVTTL clock input.
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the otuputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
PLL Bypass. When LOW, the output is driven from the VCO output.
When HIGH, the PLL is bypassed and the output frequency =
reference clock frequency/N output divider.
LVCMOS/LVTTL interface levels.
Analog supply pin.
Core supply pin.
Cr ystal oscillator interface. XTAL_OUT is the output.
XTAL_IN is the input.
Power supply ground.
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
15
Ω
typical output impedence.
Output supply pin.
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
T
ABLE
1. P
IN
D
ESCRIPTIONS
Number
1
2, 9
3
4
5
6
Name
F_SEL0
nc
nXTAL_SEL
TEST_CLK
OE
MR
Unused
Input
Input
Input
Input
Pulldown
Pulldown
Pullup
Pulldown
7
8
10
11,
12
13, 19
14, 15
17, 18
16
20
nPLL_SEL
V
DDA
V
DD
XTAL_OUT,
XTAL_IN
GND
Q3, Q2,
Q1, Q0
V
DDO
F_SEL1
Input
Power
Power
Input
Power
Output
Power
Input
Pulldown
NOTE:
Pullup
and
Pulldown
refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
T
ABLE
2. P
IN
C
HARACTERISTICS
Symbol
C
IN
C
PD
R
PULLUP
R
PULLDOWN
R
OUT
Parameter
Input Capacitance
Power Dissipation Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
V
DD
, V
DDA
, V
DDO
= 3.465V
V
DD
, V
DDA
= 3.465V, V
DDO
= 2.625V
Test Conditions
Minimum
Typical
4
TBD
TBD
51
51
15
Maximum
Units
pF
pF
pF
kΩ
kΩ
Ω
8400042AG
www.icst.com/products/hiperclocks.html
2
REV. B DECEMBER 23, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840004
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
4.6V
-0.5V to V
DD
+ 0.5 V
-0.5V to V
DD
+ 0.5V
73.2°C/W (0 lfpm)
-65°C to 150°C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics
or
AC Character-
istics
is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
θ
JA
Storage Temperature, T
STG
T
ABLE
3A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DDD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
3.135
3.135
2.375
Typical
3.3
3.3
3.3
2.5
87
8
5
Maximum
3.465
3.465
3.465
2.625
Units
V
V
V
V
mA
mA
mA
T
ABLE
3B. LVCMOS/LVTTL DC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
70°C
Symbol Parameter
V
IH
Input
High Voltage
Input
Low Voltage
Input
High Current
Input
Low Current
F_SEL1:0, nPLL_SEL,
nXTAL_SEL, OE, MR
TEST_CLK
F_SEL1:0, nPLL_SEL,
nXTAL_SEL, OE, MR
TEST_CLK
OE, F_SEL0, F_SEL1,
nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
OE, F_SEL0, F_SEL1,
nPLL_SEL, MR,
nXTAL_SEL, TEST_CLK
V
DD
= V
IN
= 3.465V
V
DD
= V
IN
= 3.465V
V
DD
= 3.465V, V
IN
= 0V
V
DD
= 3.465V, V
IN
= 0V
V
DDO
= 3.3V ± 5%
V
DDO
= 2.5V ± 5%
V
DDO
= 3.3V or 2.5V ± 5%
-150
-5
2.6
1.8
0.5
Test Conditions
Minimum Typical
2
2
-0.3
-0.3
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
1.3
5
150
Units
V
V
V
V
µA
µA
µA
µA
V
V
V
V
IL
I
IH
I
IL
V
OH
V
OL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE 1: Outputs terminated with 50
Ω
to V
DDO
/2. See Parameter Measurement Information, Output Load Test Circuit.
T
ABLE
4. C
RYSTAL
C
HARACTERISTICS
Parameter
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant cr ystal.
840004AG
www.icst.com/products/hiperclocks.html
REV. B DECEMBER 23, 2005
Test Conditions
Minimum
Typical
26.5625
Maximum
Units
MH z
Fundamental
50
7
1
Ω
pF
mW
3
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840004
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
Test Conditions
Minimum
Typical
212.5
159.375
Maximum
Units
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
1
20% to 80%
50 0
ms
ps
%
T
ABLE
5A. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= V
DDO
= 3.3V±5%, T
A
= 0°C
TO
70°C
Symbol
Parameter
f
OUT
Output Frequency
156.25
106.25
53.125
t
sk(o)
Output Skew; NOTE 1, 3
212.5MHz (637KHz - 10MHz)
159.375MHz (637KHz - 10MHz)
TBD
0.98
0.84
TBD
0.83
1.0
t
jit(Ø)
RMS Phase Jitter (Random);
NOTE 2
156.25MHz (1.875MHz - 20MHz)
106.25MHz (637KHz - 10MHz)
53.125MHz (637KHz - 10MHz)
t
L
t
R
/ t
F
PLL Lock Time
Output Rise/Fall Time
odc
Output Duty Cycle
50
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at V
DDO
/2.
NOTE 2: Please refer to the Phase Noise Plot.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
T
ABLE
5B. AC C
HARACTERISTICS
,
V
DD
= V
DDA
= 3.3V±5%, V
DDO
= 3.3V±5%
OR
2.5V±5%, T
A
= 0°C
TO
70°C
Symbol
Parameter
Test Conditions
Minimum
Typical
212.5
159.375
f
OUT
Output Frequency
156.25
106.25
53.125
t
sk(o)
Output Skew; NOTE 1, 3
212.5MHz (637KHz - 10MHz)
159.375MHz (637KHz - 10MHz)
t
jit(Ø)
RMS Phase Jitter (Random);
NOTE 2
156.25MHz (1.875MHz - 20MHz)
106.25MHz (637KHz - 10MHz)
53.125MHz (637KHz - 10MHz)
t
L
t
R
/ t
F
PLL Lock Time
Output Rise/Fall Time
20% to 80%
50 0
50
TBD
0.93
0.76
TBD
0.81
0.99
1
Maximum
Units
MHz
MHz
MHz
MHz
MHz
ps
ps
ps
ps
ps
ps
ms
ps
%
odc
Output Duty Cycle
For notes see above, Table 4A.
8400042AG
www.icst.com/products/hiperclocks.html
4
REV. B DECEMBER 23, 2005
PRELIMINARY
Integrated
Circuit
Systems, Inc.
ICS840004
F
EMTO
C
LOCKS
™ C
RYSTAL
-
TO
-
LVCMOS/LVTTL F
REQUENCY
S
YNTHESIZER
T
YPICAL
P
HASE
N
OISE AT
53.125MH
Z
@3.3V
0
-10
-20
-30
-40
-50
➤
Fibre Channel Filter
53.125MHz
RMS Phase Jitter (Random)
637KHz to 10MHz = 1.00ps (typical)
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
Raw Phase Noise Data
➤
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
➤
1k
10k
Phase Noise Result by adding
Fibre Channel Filter to raw data
100k
1M
10M
100M
O
FFSET
F
REQUENCY
(H
Z
)
T
YPICAL
P
HASE
N
OISE AT
53.125MH
Z
@2.5V
0
-10
-20
-30
-40
-50
➤
Fibre Channel Filter
53.125MHz
RMS Phase Jitter (Random)
637KHz to 10MHz = 0.99ps (typical)
N
OISE
P
OWER
dBc
Hz
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
Raw Phase Noise Data
➤
➤
Phase Noise Result by adding
Fibre Channel Filter to raw data
100k
1M
10M
100M
REV. B DECEMBER 23, 2005
O
FFSET
F
REQUENCY
(H
Z
)
840004AG
www.icst.com/products/hiperclocks.html
5
Microcontroller MCU
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