ESDM3051
5V ESD Protection Diode
Micro−Packaged Diodes for ESD Protection
The ESDM3051 is designed to protect voltage sensitive components
that require low capacitance from ESD and transient voltage events.
Excellent clamping capability, low capacitance, low leakage, and fast
response time, make these parts ideal for ESD protection on designs
where board space is at a premium.
Features
www.onsemi.com
•
•
•
•
•
•
1
2
Low Clamping Voltage
Small Body Outline Dimensions: 0.62 mm x 0.32 mm
Low Body Height: 0.3 mm
Stand−off Voltage: 5 V
IEC61000−4−2 Level 4 ESD Protection
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
USB ID Line Protection
mSD
Card Protection
Audio Line Protection
GPIO
D
M
MARKING
DIAGRAM
PIN 1
X3DFN2
CASE 152AF
= Specific Device Code
= Date Code
DM
Typical Applications
•
•
•
•
X2DFN2
CASE 714AB
JP
M
= Specific Device Code
= Date Code
JP M
MAXIMUM RATINGS
Rating
IEC 61000−4−2 (ESD)
Contact
Air
°P
D
°
R
qJA
T
J
, T
stg
T
L
Symbol
Value
±30
±30
250
400
−55 to +150
260
Unit
kV
mW
°C/W
°C
°C
Total Power Dissipation on FR−5 Board
(Note 1) @ T
A
= 25°C
Thermal Resistance, Junction−to−Ambient
Junction and Storage Temperature Range
Lead Solder Temperature − Maximum
(10 Second Duration)
ORDERING INFORMATION
Device
ESDM3051MXT5G
ESDM3051N2T5G
Package
X3DFN2
(Pb−Free)
X2DFN2
(Pb−Free)
Shipping
†
10000 / Tape &
Reel
8000 / Tape &
Reel
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected.
1. FR−5 = 1.0 x 0.75 x 0.62 in.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
See Application Note AND8308/D for further description of survivability specs.
©
Semiconductor Components Industries, LLC, 2017
1
September, 2018 − Rev. 3
Publication Order Number:
ESDM3051/D
ESDM3051
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted)
Symbol
I
PP
V
C
V
RWM
I
R
V
BR
I
T
Parameter
Maximum Reverse Peak Pulse Current
Clamping Voltage @ I
PP
Working Peak Reverse Voltage
Maximum Reverse Leakage Current @ V
RWM
Breakdown Voltage @ I
T
Test Current
I
PP
I
T
V
C
V
BR
V
RWM
I
R
I
R
V
RWM
V
BR
V
C
I
T
V
I
PP
I
*See Application Note AND8308/D for detailed explanations of
datasheet parameters.
Bi−Directional
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise specified)
Parameter
Reverse Working Voltage
Breakdown Voltage (Note 2)
Reverse Leakage Current
Clamping Voltage (Note 3)
Clamping Voltage (Note 3)
Peak Pulse Current (Note 3)
Clamping Voltage
TLP (Note 4)
Junction Capacitance
Dynamic Resistance
Insertion Loss
Symbol
V
RWM
V
BR
I
R
V
C
V
C
I
PP
V
C
C
J
R
DYN
I
T
= 1 mA
V
RWM
= 5 V
I
PP
= 1 A
I
PP
= 8 A
t
P
= 8/20
ms
I
PP
= 16 A
IEC 61000−4−2 Level 4 equivalent
(±8 kV Contact,
±15
kV Air)
9.9
7.5
21
0.11
0.01
5.1
Conditions
Min
Typ
Max
5.0
7.0
0.1
6.0
8.2
Unit
V
V
mA
V
V
A
V
pF
W
dB
V
R
= 0 V, f = 1 MHz
TLP Pulse
f = 10 MHz
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
2. Breakdown voltage is tested from pin 1 to 2 and pin 2 to 1.
3. Non−repetitive current pulse at T
A
= 25°C, per IEC61000−4−5 waveform.
4. ANSI/ESD STM5.5.1 − Electrostatic Discharge Sensitivity Testing using Transmission Line Pulse (TLP) Model.
TLP conditions: Z
0
= 50
W,
t
p
= 100 ns, t
r
= 4 ns, averaging window; t
1
= 30 ns to t
2
= 60 ns.
TYPICAL CHARACTERISTICS
40
35
30
VOLTAGE (V)
VOLTAGE (V)
0
20
40
60
80
TIME (ns)
100
120 140
25
20
15
10
5
0
−5
−20
5
0
−5
−10
−15
−20
−25
−30
−35
−40
−20
0
20
40
60
80
TIME (ns)
100
120 140
Figure 1. ESD Clamping Voltage Screenshot
Positive 8 kV Contact per IEC61000−4−2
Figure 2. ESD Clamping Voltage Screenshot
Negative 8 kV Contact per IEC61000−4−2
www.onsemi.com
2
ESDM3051
TYPICAL CHARACTERISTICS
1.E−03
1.E−04
20
1.E−05
1.E−06
1.E−07
1.E−08
1.E−09
1.E−10
1.E−11
−10
−8
−6
−4
−2
0
V
R
(V)
2
4
6
8
10
0
−5
−4
−3
−2
−1
0
1
2
3
4
5
C (pF)
I
R
(A)
15
25
10
5
V
BIAS
(V)
Figure 3. IV Characteristics
Figure 4. CV Characteristics
1
0
−1
−3
S21 (dB)
−4
−5
−6
−7
−8
−9
−10
1.0E+07
1.0E+08
FREQUENCY (Hz)
1.0E+09
CAPACITANCE (pF)
−2
80.0
70.0
60.0
50.0
40.0
30.0
20.0
10.0
0.0
0.0E+00
5.0E+08
1.0E+09
FREQUENCY
1.5E+09 2.0E+09
Figure 5. RF Insertion Loss
Figure 6. Capacitance over Frequency
20
18
10
−20
−18
10
EQUIVALENT V
IEC
(kV)
TLP CURRENT (A)
14
12
10
8
6
4
2
0
0
1
2
3
4
5
6
7
8
9
0
10
2
4
6
−14
−12
−10
−8
−6
−4
−2
0
0
1
2
3
4
5
6
7
8
9
VOLTAGE (V)
0
10
2
4
6
VOLTAGE (V)
Figure 7. Positive TLP I−V Curve
Figure 8. Negative TLP I−V Curve
www.onsemi.com
3
EQUIVALENT V
IEC
(kV)
16
TLP CURRENT (A)
8
−16
8
ESDM3051
10
9
8
7
V
C
@ I
PK
(V)
6
5
4
3
2
1
0
0
2
4
6
I
PK
(A)
8
10
12
V
C
@ I
PK
(V)
9
8
7
6
5
4
3
2
1
0
0
2
4
6
I
PK
(A)
8
10
12
Figure 9. Positive Clamping Voltage vs. Peak Pulse
Current (tp = 8/20
ms)
Figure 10. Negative Clamping Voltage vs. Peak
Pulse Current (tp = 8/20
ms)
www.onsemi.com
4
ESDM3051
IEC 61000−4−2 Spec.
Test Volt-
age (kV)
2
4
6
8
First Peak
Current
(A)
7.5
15
22.5
30
Current at
30 ns (A)
4
8
12
16
Current at
60 ns (A)
2
4
6
8
I @ 60 ns
10%
t
P
= 0.7 ns to 1 ns
I @ 30 ns
IEC61000−4−2 Waveform
I
peak
100%
90%
Level
1
2
3
4
Figure 11. IEC61000−4−2 Spec
Device
ESD Gun
Under
Test
Oscilloscope
50
W
Cable
50
W
Figure 12. Diagram of ESD Test Setup
ESD Voltage Clamping
For sensitive circuit elements it is important to limit the
voltage that an IC will be exposed to during an ESD event
to as low a voltage as possible. The ESD clamping voltage
is the voltage drop across the ESD protection diode during
an ESD event per the IEC61000−4−2 waveform. Since the
IEC61000−4−2 was written as a pass/fail spec for larger
systems such as cell phones or laptop computers it is not
clearly defined in the spec how to specify a clamping voltage
100
% OF PEAK PULSE CURRENT
90
80
70
60
50
40
30
20
10
0
0
20
t
P
t
r
at the device level. ON Semiconductor has developed a way
to examine the entire voltage waveform across the ESD
protection diode over the time domain of an ESD pulse in the
form of an oscilloscope screenshot, which can be found on
the datasheets for all ESD protection diodes. For more
information on how ON Semiconductor creates these
screenshots and how to interpret them please refer to
AND8307/D.
PEAK VALUE I
RSM
@ 8
ms
PULSE WIDTH (t
P
) IS DEFINED
AS THAT POINT WHERE THE
PEAK CURRENT DECAY = 8
ms
HALF VALUE I
RSM
/2 @ 20
ms
40
t, TIME (ms)
60
80
Figure 13. 8 X 20
ms
Pulse Waveform
www.onsemi.com
5
京公网安备 11010802033920号
EEWORLD
