PI7C9X110
PCI Express-to-PCI
Reversible Bridge
DATASHEET
Revision 4.3
May 2017
1545 Barber Lane Milpitas, CA 95035
Telephone: 408-232-9100
FAX: 408-434-1040
Internet:
http://www.diodes.com
17-0071
PI7C9X110
IMPORTANT NOTICE
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION).
Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other
changes without further notice to this document and any product described herein. Diodes Incorporated does not assume any liability arising
out of the application or use of this document or any product described herein; neither does Diodes Incorporated convey any license under
its patent or trademark rights, nor the rights of others. Any Customer or user of this document or products described herein in such
applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are
represented on Diodes Incorporated website, harmless against all damages.
Diodes Incorporated does not warrant or accept any liability whatsoever in respect of any products purchased through unauthorized sales
channel.
Should Customers purchase or use Diodes Incorporated products for any unintended or unauthorized application, Customers shall
indemnify and hold Diodes Incorporated and its representatives harmless against all claims, damages, expenses, and attorney fees arising
out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized application.
Products described herein may be covered by one or more United States, international or foreign patents pending. Product names and
markings noted herein may also be covered by one or more United States, international or foreign trademarks.
This document is written in English but may be translated into multiple languages for reference. Only the English version of this document is
the final and determinative format released by Diodes Incorporated.
LIFE SUPPORT
Diodes Incorporated products are specifically not authorized for use as critical components in life support devices or systems without the
express written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
A. Life support devices or systems are devices or systems which:
1. are intended to implant into the body, or
2. support or sustain life and whose failure to perform when properly used in accordance with instructions for use provided in
the labeling can be reasonably expected to result in significant injury to the user.
B. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause
the
failure of the life support device or to affect its safety or effectiveness.
Customers represent that they have all necessary expertise in the safety and regulatory ramifications of their life support devices or systems,
and acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their
products and any use of Diodes Incorporated products in such safety-critical, life support devices or systems, notwithstanding any devices-
or systems-related information or support that may be provided by Diodes Incorporated. Further, Customers must fully indemnify Diodes
Incorporated and its representatives against any damages arising out of the use of Diodes Incorporated products in such safety-critical, life
support devices or systems.
Copyright © 2016, Diodes Incorporated
www.diodes.com
17-0071
PI7C9X110
Rev 4.3
Page 2 of 141
www.diodes.com
May 2017
© Diodes Incorporated
PI7C9X110
REVISION HISTORY
DATE
09/08/2006
11/21/2006
03/06/2007
05/02/2007
REVISION #
2.0
2.1
2.2
2.3
DESCRIPTION
First release of 9X110 datasheet without revision suffix
Removed references to PI7C9X110A
Revised ESD ratings in “DC Specifications” section 16.2
Revised table 8-1 in section 8
Address bit[5] corrected to equal 0
Address bit[4] corrected to equal GPIO[3]
Revised logos and font types and added Industrial Temp Compliancy
Revised Industrial Temp Compliancy
Revised Minimum PCI Frequency Support to 10MHz
Added Leaded Part Number – PI7C9X110BNB
Added additional pin description to GPIO [3:0]
Revised Ordering Info Section for Leaded Part
Revised Revision ID Register definition
Updated the pin description of PCI Express Signals
PCIX Feature is removed from Datasheets
Updated Section 17 Package Information
Updated Section 1 Introduction
Updated Section 2.2 PCI Express Signals
Updated Section 7.4.38 Express Transmitter/Receiver Register – Offset 68H (bit[5:2])
Updated Section 7.5.41 Express Transmitter/Receiver Register – Offset 68H (bit[5:2])
Updated Section 7.4 PCI Configuration Registers For Transparent Bridge Mode
Updated Section 7.5 PCI Configuration Registers For Non-Transparent Bridge Mode
Updated Section 7.4 PCI Configuration Registers For Transparent Bridge Mode
Updated Section 7.5 PCI Configuration Registers For Non-Transparent Bridge Mode
Updated Section 2.5 JTAG Boundary Scan Signals
Updated Section 16.1 Absolute Maximum ratings
Updated Table 16-2 DC Electrical Characteristics
Added Table 16-4 PCI Express Interface - Differential Transmitter (TX) Output Characteristics
Added Table 16-5 PCI Express Interface - Differential Receiver (RX) Input Characteristics
Added Section 16.4 Operating Ambient Temperature
Added Table 16-4 PCIe Reference Clock Timing Parameters
11/02/2007
01/03/2008
05/16/2008
09/25/2008
08/21/2009
09/14/2009
10/10/2009
04/28/2010
03/22/2011
04/27/2011
12/07/2011
02/16/2015
04/15/2015
04/21/2016
05/12/2017
2.4
2.5
2.6
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
4.0
4.1
4.2
4.3
PREFACE
The datasheet of PI7C9X110 will be enhanced periodically when updated information is available. The technical
information in this datasheet is subject to change without notice. This document describes the functionalities of
PI7C9X110 (PCI Express Bridge) and provides technical information for designers to design their hardware using
PI7C9X110.
17-0071
PI7C9X110
Rev 4.3
Page 3 of 141
www.diodes.com
May 2017
© Diodes Incorporated
PI7C9X110
TABLE OF CONTENTS
1
INTRODUCTION ........................................................................................................................ 14
1.1
1.2
1.3
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
3
3.1
3.2
4
5
PCI EXPRESS FEATURES ................................................................................................... 14
PCI FEATURES ..................................................................................................................... 15
GENERAL FEATURES ......................................................................................................... 15
SIGNAL TYPES ..................................................................................................................... 16
PCI EXPRESS SIGNALS ...................................................................................................... 16
PCI SIGNALS ........................................................................................................................ 16
MODE SELECT AND STRAPPING SIGNALS ................................................................... 18
JTAG BOUNDARY SCAN SIGNALS .................................................................................. 18
MISCELLANEOUS SIGNALS ............................................................................................. 18
POWER AND GROUND PINS ............................................................................................. 19
PIN ASSIGNMENTS ............................................................................................................. 20
FUNCTIONAL MODE SELECTION .................................................................................... 21
PIN STRAPPING ................................................................................................................... 21
PIN DEFINITIONS ...................................................................................................................... 16
MODE SELECTION AND PIN STRAPPING .......................................................................... 21
FORWARD AND REVERSE BRIDGING ................................................................................ 22
TRANSPARENT AND NON-TRANSPARENT BRIDGING .................................................. 24
5.1
5.2
TRANSPARENT MODE ....................................................................................................... 24
NON-TRANSPARENT MODE ............................................................................................. 24
TLP STRUCTURE ................................................................................................................. 26
VIRTUAL ISOCHRONOUS OPERATION .......................................................................... 26
CONFIGURATION REGISTER MAP .................................................................................. 27
PCI EXPRESS EXTENDED CAPABILITY REGISTER MAP ............................................ 30
CONTROL AND STATUS REGISTER MAP ....................................................................... 31
PCI CONFIGURATION REGISTERS FOR TRANSPARENT BRIDGE MODE ................ 33
VENDOR ID – OFFSET 00h ................................................................................................................ 33
DEVICE ID – OFFSET 00h .................................................................................................................. 33
COMMAND REGISTER – OFFSET 04h .............................................................................................. 33
PRIMARY STATUS REGISTER – OFFSET 04h ................................................................................... 34
REVISION ID REGISTER – OFFSET 08h ........................................................................................... 35
CLASS CODE REGISTER – OFFSET 08h ........................................................................................... 35
CACHE LINE SIZE REGISTER – OFFSET 0Ch .................................................................................. 36
PRIMARY LATENCY TIMER REGISTER – OFFSET 0Ch .................................................................. 36
PRIMARY HEADER TYPE REGISTER – OFFSET 0Ch ...................................................................... 36
RESERVED REGISTERS – OFFSET 10h TO 17h ................................................................................ 36
PRIMARY BUS NUMBER REGISTER – OFFSET 18h ........................................................................ 36
6
PCI EXPRESS FUNCTIONAL OVERVIEW ........................................................................... 26
6.1
6.2
7
CONFIGURATION REGISTERS.............................................................................................. 27
7.1
7.2
7.3
7.4
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10
7.4.11
17-0071
PI7C9X110
Rev 4.3
Page 4 of 141
www.diodes.com
May 2017
© Diodes Incorporated
PI7C9X110
7.4.12
7.4.13
7.4.14
7.4.15
7.4.16
7.4.17
7.4.18
7.4.19
7.4.20
7.4.21
7.4.22
7.4.23
7.4.24
7.4.25
7.4.26
7.4.27
7.4.28
7.4.29
7.4.30
7.4.31
7.4.32
7.4.33
7.4.34
7.4.35
7.4.36
7.4.37
7.4.38
7.4.39
7.4.40
7.4.41
7.4.42
7.4.43
7.4.44
7.4.45
7.4.46
7.4.47
7.4.48
7.4.49
7.4.50
7.4.51
7.4.52
7.4.53
7.4.54
7.4.55
7.4.56
7.4.57
7.4.58
7.4.59
7.4.60
7.4.61
7.4.62
7.4.63
7.4.64
17-0071
SECONDARY BUS NUMBER REGISTER – OFFSET 18h .................................................................. 36
SUBORDINATE BUS NUMBER REGISTER – OFFSET 18h .............................................................. 36
SECONDARY LATENCY TIME REGISTER – OFFSET 18h................................................................ 37
I/O BASE REGISTER – OFFSET 1Ch .................................................................................................. 37
I/O LIMIT REGISTER – OFFSET 1Ch ................................................................................................. 37
SECONDARY STATUS REGISTER – OFFSET 1Ch ............................................................................ 37
MEMORY BASE REGISTER – OFFSET 20h ....................................................................................... 38
MEMORY LIMIT REGISTER – OFFSET 20h ...................................................................................... 38
PREFETCHABLE MEMORY BASE REGISTER – OFFSET 24h ......................................................... 39
PREFETCHABLE MEMORY LIMIT REGISTER – OFFSET 24h ........................................................ 39
PREFETCHABLE BASE UPPER 32-BIT REGISTER – OFFSET 28h................................................. 39
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER – OFFSET 2Ch ............................................... 39
I/O BASE UPPER 16-BIT REGISTER – OFFSET 30h ......................................................................... 39
I/O LIMIT UPPER 16-BIT REGISTER – OFFSET 30h........................................................................ 39
CAPABILITY POINTER – OFFSET 34h .............................................................................................. 39
EXPANSION ROM BASE ADDRESS REGISTER – OFFSET 38h ....................................................... 40
INTERRUPT LINE REGISTER – OFFSET 3Ch ................................................................................... 40
INTERRUPT PIN REGISTER – OFFSET 3Ch ..................................................................................... 40
BRIDGE CONTROL REGISTER – OFFSET 3Ch ................................................................................ 40
PCI DATA BUFFERING CONTROL REGISTER – OFFSET 40h ....................................................... 41
CHIP CONTROL 0 REGISTER – OFFSET 40h ................................................................................... 43
RESERVED REGISTER – OFFSET 44h............................................................................................... 44
ARBITER ENABLE REGISTER – OFFSET 48h ................................................................................... 44
ARBITER MODE REGISTER – OFFSET 48h ...................................................................................... 45
ARBITER PRIORITY REGISTER – OFFSET 48h ................................................................................ 45
RESERVED REGISTERS – OFFSET 4Ch – 64h .................................................................................. 46
EXPRESS TRANSMITTER/RECEIVER REGISTER – OFFSET 68h .................................................... 46
UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER – OFFSET 68h ....................... 47
RESERVED REGISTER – OFFSET 6Ch .............................................................................................. 47
EEPROM AUTOLOAD CONTROL/STATUS REGISTER – OFFSET 70h ........................................... 47
RESERVED REGISTER – OFFSET 74h............................................................................................... 48
GPIO DATA AND CONTROL REGISTER – OFFSET 78h .................................................................. 48
RESERVED REGISTER – OFFSET 7Ch .............................................................................................. 48
CAPABILITY ID REGISTER – OFFSET 80h ....................................................................................... 48
NEXT CAPABILITY POINTER REGISTER – OFFSET 80h ................................................................ 49
SECONDARY STATUS REGISTER – OFFSET 80h ............................................................................. 49
BRIDGE STATUS REGISTER – OFFSET 84h ..................................................................................... 49
UPSTREAM SPLIT TRANSACTION REGISTER – OFFSET 88h ........................................................ 51
DOWNSTREAM SPLIT TRANSACTION REGISTER – OFFSET 8Ch ................................................. 51
POWER MANAGEMENT ID REGISTER – OFFSET 90h .................................................................... 51
NEXT CAPABILITY POINTER REGISTER – OFFSET 90h ................................................................ 51
POWER MANAGEMENT CAPABILITY REGISTER – OFFSET 90h .................................................. 51
POWER MANAGEMENT CONTROL AND STATUS REGISTER – OFFSET 94h .............................. 52
PCI-TO-PCI SUPPORT EXTENSION REGISTER – OFFSET 94h ..................................................... 52
RESERVED REGISTERS – OFFSET 98h – 9Ch .................................................................................. 53
CAPABILITY ID REGISTER – OFFSET A0h ....................................................................................... 53
NEXT POINTER REGISTER – OFFSET A0h....................................................................................... 53
SLOT NUMBER REGISTER – OFFSET A0h ....................................................................................... 53
CHASSIS NUMBER REGISTER – OFFSET A0h ................................................................................. 53
SECONDARY CLOCK AND CLKRUN CONTROL REGISTER – OFFSET A4h ................................. 53
CAPABILITY ID REGISTER – OFFSET A8h ....................................................................................... 55
NEXT POINTER REGISTER – OFFSET A8h....................................................................................... 55
RESERVED REGISTER – OFFSET A8h .............................................................................................. 55
PI7C9X110
Rev 4.3
Page 5 of 141
www.diodes.com
May 2017
© Diodes Incorporated
Embedded System
京公网安备 11010802033920号
EEWORLD
