Datasheet
RX21A Group
Renesas MCUs
R01DS0129EJ0110
Rev.1.10
Aug 28, 2014
50-MHz 32-bit RX MCUs, 78 DMIPS, 24-bit
∆Σ
A/D Converter,
up to 512-KB flash memory, IrDA, 10-bit A/D, 10-bit D/A, DEU, ELC,
MPC, RTC; up to 9 comms interfaces
Features
■
32-bit RX CPU core
Max. operating frequency: 50 MHz
Capable of 78 DMIPS in operation at 50 MHz
Accumulator handles 64-bit results (for a single
instruction) from 32- × 32-bit operations
Multiplication and division unit handles 32- × 32-bit
operations (multiplication instructions take one CPU
clock cycle)
Fast interrupt
CISC Harvard architecture with 5-stage pipeline
Variable-length instructions, ultra-compact code
Memory protection unit
On-chip debugging circuit
■
Low power design and architecture
Operation from a single 1.8-V to 3.6-V supply
(2.7 V to 3.6 V for the
ΔΣ
A/D converter operating
voltage)
Deep software standby mode with RTC remaining usable
Four low power modes
■
24-bit
∆Σ
A/D Converter
SNDR = 85dB
Seven
ΔΣ
converter units available. Seven channels can
be operated simultaneously or independently.
Up to x 64 PGA gain for differential input
■
On-chip flash memory for code, no wait states
50-MHz operation, 20-ns read cycle
No wait states for reading at full CPU speed
256-K to 512-Kbyte capacities
User code programmable via the SCI
Programmable at 1.8 V
For instructions and operands
■
On-chip data flash memory
8 Kbytes
(Number of times of reprogramming: 100,000)
Erasing and programming impose no load on the CPU.
■
On-chip SRAM, no wait states
32-K to 64-Kbyte size capacities
■
DMA
DMAC: Incorporates four channels
DTC: Four transfer modes
■
Reset and supply management
Nine types of reset, including the power-on reset (POR)
Low voltage detection (LVD) with voltage settings
■
Clock functions
Frequency of external clock: Up to 20 MHz
Frequency of the oscillator for sub-clock generation:
32.768 kHz
PLL circuit input: 4 MHz to 12.5 MHz
On-chip low- and high-speed oscillators, dedicated on-
chip low-speed oscillator for the IWDT
Generation of a dedicated 32.768-kHz clock for the RTC
Clock frequency accuracy measurement circuit (CAC)
■
Real-time clock
Adjustment functions (30 seconds, leap year, and error)
Year and month display or 32-bit second display (binary
counter) is selectable
Time capture on event-signal input through external pins
RTC capable of initiating return from deep software
standby mode
PLQP0100KB-A
PLQP0080KB-A
PLQP0064KB-A
PTLG0100JA-A
14 × 14 mm, 0.5-mm pitch
12 × 12 mm, 0.5-mm pitch
10 × 10 mm, 0.5-mm pitch
7×7mm, 0.65-mm pitch
■
Independent watchdog timer
125-kHz on-chip oscillator produces a dedicated clock
signal to drive IWDT operation.
■
Useful functions for IEC60730 compliance
Self-diagnostic and disconnection-detection assistance
functions for the A/D converter, clock-frequency
accuracy-measurement circuit, independent watchdog
timer, functions to assist in RAM testing, etc.
■
Up to nine communications channels
SCI with many useful functions (up to five channels)
Asynchronous mode, clock synchronous mode, smart
card interface
IrDA Interface (one channel, in cooperation with the
SCI5)
I
2
C bus interface: Transfer at up to 400 kbps, capable of
SMBus operation (two channels)
RSPI (two channels)
■
Up to 14 extended-function timers
16-bit MTU: input capture, output compare,
complementary PWM output, phase counting mode
(six channels)
8-bit TMR (four channels)
16-bit compare-match timers (four channels)
■
10-bit A/D converter
Conversion time 2.0
μs
Self-diagnostic function and analog input disconnection
detection assistance function
■
10-bit D/A converter
■
Analog comparator
■
General I/O ports
5-V tolerant, open drain, input pull-up, switching of
driving ability
■
MPC
Multiple locations are selectable for I/O pins of
peripheral functions
■
ELC
Module operation can be initiated by event signals
without going through interrupts.
Modules can operate while the CPU is sleeping.
■
DEU
Encryption and decryption of AES
128-, 192-, or 256-bit key length
ECB/CBC Mode
■
Temperature sensor
■
Operating temp. range
40C
to +85C
40C
to +105C
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 1 of 132
RX21A Group
1. Overview
1.
1.1
Overview
Outline of Specifications
Table 1.1
shows the outline of the specifications and
Table 1.2
shows the comparison of the functions of products in
different packages.
Table 1.1
is for products with the greatest number of functions, so numbers of peripheral modules and channels will
differ in accord with the package. For details, see
Table 1.2, Comparison of Functions for Different Packages.
Table 1.1
Classification
CPU
Outline of Specifications (1 / 4)
Module/Function
CPU
Description
Maximum operating frequency: 50 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per state (cycle of the system clock)
Address space: 4-Gbyte linear
Register set
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32 x 32
64 bits
On-chip divider: 32 / 32
32 bits
Barrel shifter: 32 bits
Memory protection unit (MPU)
Memory
ROM
Capacity: 256 K/384 K/512 Kbytes
50 MHz, no-wait memory access
On-board programming: 3 types
Capacity:32 K/64 Kbytes
50 MHz, no-wait memory access
Capacity: 8 Kbytes
Number of times for programming/erasing: 100,000
Single-chip mode
Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
PLL frequency synthesizer, and IWDT-dedicated on-chip oscillator
Oscillation stop detection
Measuring circuit for accuracy of clock frequency (clock-accuracy check: CAC)
Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 50 MHz (at max.)
Peripheral modules run in synchronization with the peripheral module clock (PCLK):25 MHz (at max.)
The flash peripheral circuit runs in synchronization with the flash peripheral clock (FCLK): 25 MHz (at
max.)
RES# pin reset, power-on reset, voltage monitoring reset, watchdog timer reset, independent watchdog
timer reset, deep software standby reset, and software reset
RAM
E2 DataFlash
MCU operating mode
Clock
Clock generation circuit
Reset
Voltage detection
Voltage detection circuit
(LVDAa)
When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 0 is capable of selecting the detection voltage from 2 levels
Voltage detection circuit 1 is capable of selecting the detection voltage from 9 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 9 levels
Module stop function
Four low power consumption modes
Sleep mode, all-module clock stop mode, software standby mode, and deep software standby mode
High-speed operating mode, middle-speed operating mode 1A, middle-speed operating mode 1B,
middle-speed operating mode 2A, middle-speed operating mode 2B, low-speed operating mode 1, low-
speed operating mode 2
Interrupt vectors: 122
External interrupts: 9 (NMI and IRQ0 to IRQ7 pins)
Non-maskable interrupts: 6 (the NMI pin, oscillation stop detection interrupt, voltage monitoring 1
interrupt, voltage monitoring 2 interrupt, WDT interrupt, and IWDT interrupt)
16 levels specifiable for the order of priority
Low power
consumption
Low power consumption
facilities
Function for lower operating
power consumption
Interrupt
Interrupt controller (ICUb)
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
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RX21A Group
Table 1.1
Classification
DMA
1. Overview
Outline of Specifications (2 / 4)
Module/Function
DMA controller (DMACA)
Description
4 channels
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Software trigger, external interrupts, and interrupt requests from peripheral
functions
Three transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Interrupts
Chain transfer function
100-pin/80-pin/64-pin
I/O pin: 66/51/38
Input: 1/1/1
Pull-up resistors: 66/51/38
Open-drain outputs: 47/37/28
5-V tolerance: 6/6/2
Event signals of 69 types can be directly connected to the module
Operations of timer modules are selectable at event input
Capable of event link operation for ports B and E
Capable of selecting input/output function from multiple pins
(16 bits x 6 channels) x 1 unit
Up to 16 pulse-input/output lines and three pulse-input lines are available with six 16-bit timer
channels.
Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
Input capture function
21 output compare/input capture registers
Pulse output mode
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Generation of triggers for A/D converter conversion
Controls the high-impedance state of the MTU’s waveform output pins
(8 bits x 2 channels) x 2 units
Select from among seven internal clock signals (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64,
PCLK/1024, PCLK/8192) and one external clock signal
Capable of output of pulse trains with desired duty cycles or of PWM signals
The 2 channels of each unit can be cascaded to create a 16-bit timer
Capable of generating baud-rate clocks for SCI5 and SCI6
(16 bits x 2 channels) x 2 units
Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
14 bits x 1 channel
Select from among 6 counter-input clock signals (PCLK/4, PCLK/64, PCLK/128, PCLK/512,
PCLK/2048, PCLK/8192)
14 bits x 1 channel
Counter-input clock: IWDT-dedicated on-chip oscillator
Frequency divided by 1, 16, 32, 64, 128, or 256
Clock source: Sub-clock
Time count or 32-bit binary count in second units basis selectable
Time/calendar
Interrupt sources: Alarm interrupt, periodic interrupt, and carry interrupt
Time-capture facility for three values
Data transfer controller
(DTCa)
I/O ports
General I/O ports
Event link controller (ELC)
Multi-function pin controller (MPC)
Timers
Multi-function timer pulse
unit 2 (MTU2a)
Port output enable2
(POE2a)
8-bit timer (TMR)
Compare match timer
(CMT)
Watchdog timer (WDTA)
Independent watchdog
timer (IWDTa)
Realtime clock (RTCc)
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 3 of 132
RX21A Group
Table 1.1
Classification
Communication
function
1. Overview
Outline of Specifications (3 / 4)
Module/Function
Serial communications
interfaces (SCIc)
Description
5 channels (channel 1, 5, 6, 8, 9) (including one channel for IrDA)
Serial communications modes:
Asynchronous, clock synchronous, and smart-card interface
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from TMR timers (SCI5 and SCI6)
Simple IIC
Simple SPI
1 channel (SCI5 is used)
Supports encoding/decoding the waveforms conforming to the IrDA specification version 1.0
2 channels
Communications formats:
I
2
C bus format/SMBus format
Master/slave selectable
Supports the fast mode
2 channels
Transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI
clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock-
synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Choice of LSB-first or MSB-first transfer
The number of bits in each transfer can be changed to any number of bits from 8 to 16, 20, 24, or 32
bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each frame
having up to 32 bits)
Double buffers for both transmission and reception
7 channels: 4-channel differential input for current; 3-channel single-ended input for voltage
x 1 to x 64 PGA for differential input side for current and x 1 to x 4 PGA for single-ended input side for
voltage
Minimum conversion time: 81.92
μs
(A/D conversion clock: 25 MHz)
10 bits (7 channels x 1 unit)
10-bit resolution
Conversion time: 2.0
μs
per channel (A/D conversion clock: 25 MHz)
Operating modes
Scan mode (single scan mode and continuous scan mode)
Sample-and-hold function
Self-diagnosis for the A/D converter
Assistance in detecting disconnected analog inputs
A/D conversion start conditions
Conversion can be started by software, a conversion start trigger from a timer (MTU), an external
trigger signal, a temperature sensor or ELC.
IrDA interface (IRDA)
I
2
C bus interface (RIIC)
Serial peripheral
interface (RSPI)
24-bit
∆Σ
A/D converter (DSAD)
10-bit A/D converter (AD)
Temperature sensor (TEMPSa)
D/A converter (DA)
Outputs the voltage that changes depending on the temperature
PGA gain switchable: Three levels according to the voltage range
2 channels
10-bit resolution
Output voltage: 0 V to VREFH
CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X
8
+ X
2
+ X + 1, X
16
+ X
15
+ X
2
+ 1, or X
16
+ X
12
+ X
5
+ 1
Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.
Encryption and decryption of AES
128-, 192-, or 256-bit key length
ECB or CBC mode
2 channels
Comparison of reference voltage and analog input voltage
2 channels
Comparison of reference voltage and analog input voltage
Comparison, addition, and subtraction of 16-bit data
VCC = 1.8 to 3.6 V: 25 MHz, VCC = 2.7 to 3.6 V: 50 MHz
8.6mA@50MHz (typ)
D version: –40 to +85°C, G version: –40 to +105°C*
2
,
*
3
CRC calculator (CRC)
Data encryption unit (DEU)*
1
Comparator A (CMPA)
Comparator B (CMPB)
Data operating circuit (DOC)
Power supply voltage/ Operating frequency
Supply current
Operating temperature
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 4 of 132
RX21A Group
Table 1.1
Classification
Package
1. Overview
Outline of Specifications (4 / 4)
Module/Function
Description
100-pin LQFP (PLQP0100KB-A) 14 x 14 mm, 0.5-mm pitch
80-pin LQFP (PLQP0080KB-A) 12 x 12mm, 0.5-mm pitch
64-pin LQFP (PLQP0064KB-A) 10 x 10mm, 0.5-mm pitch
100-pin TFLGA (PTLG0100JA-A) 7 × 7 mm, 0.65-mm pitch
E1 emulator (FINE interfaces)
On-chip debugging system
Note 1. Contact a Renesas Electronics sales office for more information.
Note 2. Please contact Renesas Electronics sales office for derating of operation under Ta = +85°C to +105°C. Derating is the
systematic reduction of load for the sake of improved reliability.
Note 3. The unique ID specification and the calibration functions of the temperature sensor and the 24-Bit
∆Σ
A/D converter of these
products differ from other products. For details, see following sections in the
RX21A Group User’s Manual: Hardware.
Section 34.2.11,
∆Σ
A/D Input Impedance Calibration Data Register (DSADIIC)
Section 34.2.12,
∆Σ
A/D Gain Calibration Data Registers (DSADGmXn) (m = 0 to 6, n = 1, 2, 4, 8, 16, and 32)
Section 37.2.2, Temperature Sensor Calibration Data Registers (TSCDRn) (n = 0,1,3)
Section 37.3, Using the Temperature Sensor
Section 42.2.15, Unique ID Registers (UIDRn) (n = 0 to 3)
Table 1.2
Comparison of Functions for Different Packages
RX21A Group
100 Pins
80 Pins
NMI, IRQ0 to IRQ7
64 Pins
NMI, IRQ0 to IRQ2,
IRQ4 to IRQ7
Module/Functions
Interrupt
DMA
External interrupts
DMA controller
Data transfer controller
Timers
Multi-function timer pulse unit 2
Port output enable 2
8-bit timer
Compare match timer
Realtime clock
Watchdog timer
Independent watchdog timer
Communication
function
Serial communications interface
I
2
C bus interface
Serial peripheral interface
24-bit
∆Σ
A/D converter
10-bit A/D converter
4 channels (DMAC0 to DMAC3)
Supported
6 channels (MTU0 to MTU5)
POE0# to POE3#, POE8#
2 channels × 2 units
2 channels × 2 units
Supported
Supported
Supported
5 channels (SCI1, 5, 6, 8, 9) (including one channel for IrDA)
2 channels
2 channels
7 channels
4 channels
7 channels
(AN0 to AN6)
Supported
2 channels
Supported
Supported
Supported
2 channels
2 channels
100-pin LQFP
100-pin TFLGA
80-pin LQFP
64-pin LQFP
1 channel
—
3 channels
4 channels
(AN0, AN1, AN4,
AN5)
1 channel
Temperature sensor
D/A converter
CRC calculator
Data encryption unit
Event link controller
Comparator A
Comparator B
Package
R01DS0129EJ0110 Rev.1.10
Aug 28, 2014
Page 5 of 132
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