Jitter Attenuator & FemtoClock NG
®
Multiplier
813N322I-02
Datasheet
General Description
The 813N322I-02 device uses IDT's fourth generation FemtoClock
®
NG technology for optimal high clock frequency and low phase noise
performance, combined with a low power consumption and high
power supply noise rejection. The 813N322I-02 is a PLL based
synchronous multiplier that is optimized for Ethernet to SONET/PDH
clock jitter attenuation and frequency translation.
The 813N322I-02 is a fully integrated Phase Locked loop utilizing a
FemtoClock NG Digital VCXO that provides the low jitter, high
frequency SONET/PDH output clock that easily meets OC-48 jitter
requirements. This VCXO technology simplifies PLL design by
replacing the pullable crystal requirement of analog VCXOs with a
fixed 27MHz generator crystal. Jitter attenuation down to 10Hz is
provided by an external loop filter. Pre-divider and output divider
multiplication ratios are selected using device selection control pins.
The multiplication ratios are optimized to support most common
clock rates used in PDH, SONET and Ethernet applications. The
device requires the use of an external, inexpensive fundamental
mode 27MHz crystal. The device is packaged in a space-saving
32-VFQFN package and supports industrial temperature range.
Features
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Fourth Generation FemtoClock® NG technology
Two LVPECL output pairs
Each output supports independent frequency selection at
19.44MHz, 77.76MHz, 155.52MHz and 622.08MHz
Two differential inputs support the following input types: LVPECL,
LVDS, LVHSTL, HCSL
Accepts input frequencies from 8kHz to 156.25MHz including
8kHz,19.44MHz, 25MHz, 62.5MHz, 77.76MHz, 125MHz,
155.52MHz and 156.25MHz
Crystal interface designed for a 27MHz, 10pF parallel resonant
crystal
Attenuates the phase jitter of the input clock by using a low-cost
fundamental mode crystal
Customized settings for jitter attenuation and reference tracking
using an external loop filter connection
FemtoClock NG frequency multiplier provides low jitter, high
frequency output
Absolute pull range: ±50ppm
Power supply noise rejection (PSNR): -95dB (typical)
FemtoClock NG VCXO frequency: 2488.32MHz
RMS phase jitter @ 155.52MHz, using a 27MHz crystal
(12kHz – 20MHz): 0.674ps (typical)
3.3V supply voltage
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Pin Assignment
XTAL_OUT
XTAL_IN
nCLK0
nCLK1
CLK0
CLK1
V
CCX
32 31 30 29 28 27 26 25
LF1
LF0
1
2
24
V
EE
V
CC
23 nQB
22
21
QB
V
CCO
ISET 3
V
EE
4
CLK_SEL
V
CC
5
6
20 nQA
19 QA
18
17
9
PDSEL_2
RESERVED 7
V
EE
8
10 11 12 13 14 15 16
ODBSEL_1
ODBSEL_0
ODASEL_1
PDSEL_1
PDSEL_0
V
CC
V
CCA
V
EE
ODASEL_0
813N322I-02
32 Lead VFQFN
5mm x 5mm x 0.925mm package body
K Package
Top View
©2016 Integrated Device Technology, Inc.
1
Revision C, February 26, 2016
813N322I-02 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Descriptions
Number
1, 2
3
4, 8, 18, 24
5
6, 12, 27
7
9,
10,
11
13
14,
15
16,
17
19, 20
21
22, 23
25
26
28
29
30,
31
32
Name
LF1, LF0
ISET
V
EE
CLK_SEL
V
CC
RESERVED
PDSEL_2,
PDSEL_1,
PDSEL_0
V
CCA
ODBSEL_1,
ODBSEL_0
ODASEL_1,
ODASEL_0
QA, nQA
V
CCO
QB, nQB
nCLK1
CLK1
nCLK0
CLK0
XTAL_OUT,
XTAL_IN
V
CCX
Type
Analog
Input/Output
Analog
Input/Output
Power
Input
Power
Reserve
Input
Power
Input
Input
Output
Power
Output
Input
Input
Input
Input
Input
Power
Pullup/
Pulldown
Pulldown
Pullup/
Pulldown
Pulldown
Pulldown
Pulldown
Pullup
Pulldown
Description
Loop filter connection node pins. LF0 is the output. LF1 is the input.
Charge pump current setting pin.
Negative supply pins.
Input clock select. When HIGH selects CLK1, nCLK1. When LOW, selects
CLK0, nCLK0. LVCMOS / LVTTL interface levels.
Core supply pins.
Reserve pin.
Pre-divider select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
Analog supply pin.
Frequency select pins for Bank B output. See Table 3B.
LVCMOS/LVTTL interface levels.
Frequency select pins for Bank A output. See Table 3B.
LVCMOS/LVTTL interface levels.
Differential Bank A clock outputs. LVPECL interface levels.
Output supply pin.
Differential Bank B clock outputs. LVPECL interface levels.
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Non-inverting differential clock input.
Inverting differential clock input. V
CC
/2 bias voltage when left floating.
Non-inverting differential clock input.
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Power supply pin for the crystal oscillator
NOTE:
Pullup and Pulldown
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLUP
R
PULLDOWN
Parameter
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
Test Conditions
Minimum
Typical
3.5
51
51
Maximum
Units
pF
k
k
©2016 Integrated Device Technology, Inc.
3
Revision C, February 26, 2016
FPGA/CPLD
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