ZSP540 - Highly Efficient
Quad-MAC DSP Core
O V E RV I E W
The ZSP540 processor core is a high-performance/power-efficient Quad-
MAC/Six-ALU implementation of the ZSP G2 architecture. The ZSP540 utilizes a
16-bit architecture with extensive 32-bit capabilities and sets an unmatched
balance of performance/power/size and memory utilization efficiency. The
®
C O R E F E AT U R E S
• Quad-MAC/Six-ALU DSP core
• 4+1 instructions per cycle
• Up to 350MHz, 8-stage pipeline design
• Up to 1750 million instructions/sec
• Dual 64-bit wide Load/Store data ports
• Z.Turbo coprocessor extensions capable
Z.Turbo feature provides the SOC designer with the option to extend the ZSP540
Instruction Set and the ability to add application-specific acceleration logic.
TARGET MARKETS
•
2.5/3G wireless baseband processing
•
Multimedia wireless and mobile devices
•
Cable/xDSL
•
Wireless LAN (WLAN)
•
Set-top box and home gateways
•
Multi-channel Voice Over IP (VoIP)
•
Software Defined Radio (SDR)
• 24-bit address space
• HW managed instructions scheduling
• HW/SW controlled power management
• Real-time trace and profiling capability
• Full AMBA/AHB support (optional)
• JTAG debug interface
• Static, single phase clocked design
• Compatible with all other ZSP cores
A P P L I C AT I O N B E N E F I T S
•
High-performance DSP capabilities
•
Excellent power/cost/speed balance
•
Excellent multimedia audio/video processing
•
Power efficient baseband processing performance
•
DSP and system control functions handling capabilities
A R C H I T E C T U R E F E AT U R E S
• Embedded control processing efficiency
• 32-bit addressing capabilities
• 16 and 32-bit standard instruction set
• Extensive 32-bit and 40-bit support
• Easy to program instruction set
Prefetch Unit (PFU)
128-bit
Instruction Cache
Instruction
Sequence Unit
(ISU)
Pipeline
Control Unit
(PCU)
Interrupt Control
• Load/store register based instructions
• Outstanding code density
• User extensible instruction set
64-bit
64-bit
Load/Store Unit (LSU)
Dual AGU
Co-Processor IF
Register File
Debug IF
File
S U P P O RT
• Highly optimized C-compiler
• Multimedia, voice and wireless experts
• Local support by ZSP solution experts
Bypass Logic
Timers
Multiply/ALU Unit 0
40-bit
ALU
16x16
MAC
16x16
MAC
Multiply/ALU Unit 1
40-bit
ALU
16x16
MAC
16x16
MAC
ALU Unit
16-bit
ALU
16-bit
ALU
ZSP540 Highly Efficient Quad-MAC DSP Core
ZSP540 QUAD-MAC DSP PROCESSING SOLUTION
LSI Logic ZSP cores are licensable and available as a fully synthesizable and
technology independent. The ZSP Cores have been proven in ASICs and are also
available as standard general-purpose DSP and Application Specific Standard
Products (ASSP) from LSI Logic and licensees of the ZSP cores.
The ZSP540 is power-efficient/high-performance Quad-MAC DSP core
implementation of the ZSP G2 architecture version and is software compatible
with all other ZSP cores enabling code reuse and effortless design migration
and scalability.
The ZSP540 features instruction grouping, instruction parallelism and pipeline control
all done by hardware making it seamless and easy to program. Highly optimized
C-Compilers are available minimizing the need for assembly level programming.
For more information please call:
LSI Logic Corporation
Headquarters
1621 Barber Lane
Milpitas, CA 95035
Tel: 866.574.5741
(within U.S. and Canada)
1.408.954.3108
(outside U.S. and Canada)
Technical Support: 800.633.4545
Corporate Website
www.lsilogic.com
Sales Office Locations
www.lsilogic.com/contacts
Additional information on the
ZSP540 is available at:
http://www.zsp.com/zsp540.html
S O C I N T E G R AT I O N S U P P O RT
•
ZSP cores are available as a synthesizable, fully static/single-phased design
•
AMBA/AHB (optional) or native ZSP bus interfaces are available
•
Co-verification and System modeling support available by various providers
A V A I L A B L E G 2 S O F T WA R E D E V E L O P M E N T S O L U T I O N S
•
Highly optimized development kits are available from LSI Logic and Green Hills
•
Multi-core ARM/ZSP support is available through Green Hill and ARM’s RealView
•
JTAG probes for single/multi-core support available from various providers
•
Embedded real-time trace and application profiling supported
•
ZOpen
™
software development framework enables rapid integration and
LSI Logic logo design, ZOpen and ZSP are
trademarks or registered trademarks of LSI
LogicCorporation. AMBA is a registered trademark
ofARM Ltd. All other brand and product names
maybe trademarks of their respective companies.
LSI Logic Corporation reserves the right to
makechanges to any products and services herein
at anytime without notice. LSI Logic does not
assume anyresponsibility or liability arising out of
theapplication or use of any product or
servicedescribed herein, except as expressly
agreed to inwriting by LSI Logic; nor does the
purchase, lease,or use of a product or service from
LSI Logicconvey a license under any patent
rights,copyrights, trademark rights, or any other of
theintellectual property rights of LSI Logic or of
thirdparties.
Copyright ©2004 by LSI Logic Corporation.
All rights reserved.
reuse of software modules developed by different 3rd parties
A V A I L A B L E G 2 H A R D WA R E D E V E L O P M E N T S O L U T I O N S
•
Architecture evaluation boards
•
Standalone FPGA prototyping boards
•
ARM Integrator core modules available
•
Multi-media audio/video development platform
•
Audio development platform
S O F T WA R E C O M PA T I B L E Z S P C O R E S
CORE
ZSP200
ZSP400
ZSP500
ZSP540
ZSP600
#MACs
#ALUs
Inst./Cycle
Max Freq
(MHz@0.13u)
Single
Dual
2+1
220
Dual
Dual
4-issue
220
Dual
Triple
4-issue
350
Quad
Six
4+1
350
Quad
Six
6-issue
300
Order No. R20101
1004.LR.Web - Printed in USA
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