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TC7SH86F,LJ(CT

Description
IC GATE XOR 1CH 2-INP SMV
Categorylogic    logic   
File Size157KB,7 Pages
ManufacturerToshiba Semiconductor
Websitehttp://toshiba-semicon-storage.com/
Environmental Compliance
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TC7SH86F,LJ(CT Overview

IC GATE XOR 1CH 2-INP SMV

TC7SH86F,LJ(CT Parametric

Parameter NameAttribute value
Is it Rohs certified?conform to
MakerToshiba Semiconductor
package instructionTSOP, TSOP5/6,.11,37
Reach Compliance Codeunknown
Factory Lead Time12 weeks
JESD-30 codeR-PDSO-G5
Load capacitance (CL)50 pF
Logic integrated circuit typeXOR GATE
MaximumI(ol)0.004 A
Number of terminals5
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeTSOP
Encapsulate equivalent codeTSOP5/6,.11,37
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE
method of packingTAPE AND REEL
power supply2/5.5 V
Prop。Delay @ Nom-Sup16.5 ns
Certification statusNot Qualified
Schmitt triggerNO
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal formGULL WING
Terminal pitch0.95 mm
Terminal locationDUAL
TC7SH86F
CMOS Digital Integrated Circuits Silicon Monolithic
TC7SH86F
1. Functional Description
2-Input Exclusive-OR Gate
2. Features
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
AEC-Q100 (Rev. H) (Note 1)
Wide operating temperature range: T
opr
= -40 to 125
(Note 2)
High speed operation: t
pd
= 4.8 ns (typ.) (V
CC
= 5.0 V, C
L
= 15 pF)
Low power dissipation: I
CC
= 2.0
µA
(max) (T
a
= 25
)
High noise immunity: V
NIH
= V
NIL
= 28 % V
CC
(min)
5.5 V tolerant inputs
Balanced Propagation Delay: t
PLH
t
PHL
Wide operating voltage range: V
CC
= 2.0 to 5.5 V
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales
representative.
Note 2: For devices with the ordering part number ending in J(CT. T
opr
= -40 to 85
for the other devices.
3. Packaging
SMV
Start of commercial production
©2017
Toshiba Electronic Devices & Storage Corporation
1
1994-06
2017-12-21
Rev.3.0
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