19-0876; Rev 1; 5/96
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
_______________General Description
Maxim’s MX7575/MX7576 are high-speed (5µs/10µs),
microprocessor (µP) compatible, 8-bit analog-to-digital
converters (ADCs). The MX7575 provides an on-chip
track/hold function that allows full-scale signals up to
50kHz (386mV/µs slew rate) to be acquired and digi-
tized accurately. Both ADCs use a successive-approxi-
mation technique to achieve their fast conversions and
low power dissipation. The MX7575/MX7576 operate
with a +5V supply and a 1.23V external reference. They
accept input voltages ranging from 0V to 2V
REF
.
The MX7575/MX7576 are easily interfaced to all popu-
lar 8-bit µPs through standard
CS
and
RD
control sig-
nals. These signals control conversion start and data
access. A
BUSY
signal indicates the beginning and
end of a conversion. Since all the data outputs are
latched and three-state buffered, the MX7575/MX7576
can be directly tied to a µP data bus or system l/O port.
Maxim also makes the
MAX165,
a plug-in replacement
for the MX7575 with an internal 1.23V reference. For
applications that require a differential analog input and
an internal reference, the
MAX166
is recommended.
____________________________Features
o
Fast Conversion Time:
5µs (MX7575)
10µs (MX7576)
MX7575/MX7576
o
Built-In Track/Hold Function (MX7575)
o
Low Total Unadjusted Error (±1LSB max)
o
50kHz Full-Power Signal Bandwidth (MX7575)
o
Single +5V Supply Operation
o
8-Bit µP Interface
o
100ns Data-Access Time
o
Low Power: 15mW
o
Small-Footprint Packages
______________Ordering Information
PART
MX7575JN
TEMP. RANGE
0°C to +70°C
PIN-PACKAGE
18 Plastic DIP
INL
(LSB)
±1
±1/2
±1
±1/2
±1
±1/2
±1
±1
±1/2
________________________Applications
Digital Signal Processing
High-Speed Data Acquisition
Telecommunications
Audio Systems
High-Speed Servo Loops
Low-Power Data Loggers
MX7575KN
0°C to +70°C
18 Plastic DIP
MX7575JCWN
0°C to +70°C
18 Wide SO
MX7575KCWN
0°C to +70°C
18 Wide SO
MX7575JP
0°C to +70°C
20 PLCC
MX7575KP
0°C to +70°C
20 PLCC
MX7575J/D
0°C to +70°C
Dice*
MX7575AQ
-25°C to +85°C
18 CERDIP**
MX7575BQ
-25°C to +85°C
18 CERDIP**
Ordering Information continued at end of data sheet.
* Contact factory for dice specifications.
** Contact factory for availability.
_________________Pin Configurations
TOP VIEW
CS 1
RD 2
TP (MODE) 3
BUSY 4
CLK 5
D7 (MSB) 6
D6 7
D5
8
18 V
DD
17 REF
_______________Functional Diagrams
V
DD
18
16
MX7575
AIN
MX7575
MX7576
TRACK/
HOLD
COMP
16 AIN
15 AGND
14 D0 (LSB)
13 D1
12 D2
11 D3
10 D4
AGND 15
REF 17
CLK
5
CLOCK
OSCILLATOR
DAC
SAR
6
LATCH AND
THREE-STATE
OUTPUT DRIVERS
14
9
DGND
D7
D0
DGND 9
CS
RD
TP
1
2
3
CONTROL
LOGIC
.
.
( ) ARE FOR MX7576 ONLY.
DIP/SO
Pin Configurations continued at end of data sheet.
4
BUSY
Functional Diagrams continued at end of data sheet.
________________________________________________________________
Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
MX7575/MX7576
ABSOLUTE MAXIMUM RATINGS
V
DD
to AGND...............................................................-0.3V, +7V
V
DD
to DGND ..............................................................-0.3V, +7V
AGND to DGND ...............................................-0.3V, V
DD
+ 0.3V
Digital Input Voltage to DGND
(CS,
RD,
TP, MODE) ......................................-0.3V, V
DD
+ 0.3V
Digital Output Voltage to DGND
(BUSY, D0–D7) ..............................................-0.3V, V
DD
+ 0.3V
CLK Input Voltage to DGND ............................-0.3V, V
DD
+ 0.3V
REF to AGND ...................................................-0.3V, V
DD
+ 0.3V
AIN to AGND....................................................-0.3V, V
DD
+ 0.3V
Continuous Power Dissipation (T
A
= +70°C)
Plastic DIP (derate 11.11mW/°C above +70°C) ...............889mW
Wide SO (derate 9.52mW/°C above +70°C)..................762mW
CERDIP (derate 10.53mW/°C above +70°C) .................842mW
PLCC (derate 10.00mW/°C above +70°C) ....................800mW
Operating Temperature Ranges
MX757_J/K ............................................................0°C to +70°C
MX757_A/B ........................................................-25°C to +85°C
MX757_JE/KE ....................................................-40°C to +85°C
MX757_S/T.......................................................-55°C to +125°C
Storage Temperature Range .............................-65°C to +160°C
Lead Temperature (soldering,10sec) ..............................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +5V; V
REF
= 1.23V; AGND = DGND = 0V; f
CLK
= 4MHz external for MX7575; f
CLK
= 2MHz external for MX7576;
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
ACCURACY
Resolution
Total Unadjusted Error
Relative Accuracy
No-Missing-Codes Resolution
Full-Scale Error
Full-Scale Tempco
Offset Error (Note 1)
Offset Tempco
ANALOG INPUT
Voltage Range
DC Input Impedance
Slew Rate, Tracking
Signal-to-Noise Ratio (Note 2)
REFERENCE INPUT
Reference Voltage
Reference Current
LOGIC INPUTS
CS
,
RD
, MODE
Input Low Voltage
Input High Voltage
Input Current
Input Capacitance (Note 2)
V
REF
I
REF
V
INL
V
INH
I
IN
C
IN
V
IN
= 0V or V
DD
T
A
= +25°C
T
A
= T
MIN
to T
MAX
2.4
±1
±10
10
±5% variation for specified performance
1.23
500
0.8
V
µA
V
V
µA
pF
SNR
MX7575
MX7575, V
IN
= 2.46V
p-p
at 10kHz, Figure 13
45
1LSB = 2V
REF
/256
0
10
0.386
2V
REF
V
MΩ
V/µs
dB
±5
±5
±1/2
TUE
INL
MX757_K/B/T
MX757_J/A/S
MX757_K/B/T
MX757_J/A/S
8
±1
8
±1
±2
±1/2
±1
Bits
LSB
LSB
Bits
LSB
ppm/°C
LSB
ppm/°C
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
_______________________________________________________________________________________
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +5V; V
REF
= 1.23V; AGND = DGND = 0V; f
CLK
= 4MHz external for MX7575; f
CLK
= 2MHz external for MX7576;
T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
PARAMETER
CLOCK
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
LOGIC OUTPUTS (D0–D7,
BUSY
)
Output Low Voltage
Output High Voltage
Floating State Leakage Current
Floating State Output
Capacitance (Note 2)
CONVERSION TIME (Note 3)
Conversion Time with
External Clock
Conversion Time with
Internal Clock
POWER REQUIREMENTS (Note 4)
Supply Voltage
V
DD
Supply Current
Power Dissipation
Power-Supply Rejection
Note 1:
Note 2:
Note 3:
Note 4:
I
DD
MX7575: f
CLK
= 4MHz
MX7576: f
CLK
= 2MHz
Using recommended
clock components:
R
CLK
= 100kΩ,
C
CLK
= 100pF;
T
A
= +25°C
MX7575
MX7576
5
10
5
10
15
µs
30
µs
V
OL
V
OH
I
SINK
= 1.6mA
I
SOURCE
= 40µA
V
OUT
= 0V to V
DD
, D0–D7
D0–D7
T
A
= +25°C
T
A
= T
MIN
to T
MAX
4.0
±1
±10
10
0.4
V
V
µA
pF
V
INL
V
INH
I
INL
I
INH
V
IN
= 0V
V
IN
= V
DD
MX757_J/A/K/B
MX757_S/T
MX757_J/A/K/B
MX757_S/T
2.4
700
800
700
800
0.8
V
V
µA
µA
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
MX7575/MX7576
±5% for specified performance
MX757_J/A/K/B
MX757_S/T
4.75V < V
DD
< 5.25V
5
3
15
V
6
7
±1/4
mA
mW
LSB
Offset Error is measured with respect to an ideal first-code transition that occurs at 1/2LSB.
Sample tested at +25°C to ensure compliance.
Accuracy may degrade at conversion times other than those specified.
Power-supply current is measured when MX7575/MX7576 are inactive, i.e.:
For MX7575
CS
=
RD
=
BUSY
= high;
For MX7576
CS
=
RD
=
BUSY
= MODE = high.
_______________________________________________________________________________________
3
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
MX7575/MX7576
TIMING CHARACTERISTICS (Note 5)
(V
DD
= +5V, V
REF
= 1.23V, AGND = DGND = 0V.)
T
A
= +25°C
PARAMETER
CS
to
RD
Setup Time
RD
to
BUSY
Propagation Time
Data-Access Time after
RD
RD
Pulse Width
CS
to
RD
Hold Time
Data-Access Time after
BUSY
Data-Hold Time
BUSY
to
CS
Delay
SYMBOL
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
(Note 6)
(Note 7)
10
0
(Note 6)
100
0
80
80
10
0
CONDITIONS
MIN
0
100
100
100
0
80
80
10
0
ALL
MAX
0
100
100
120
0
100
100
MIN
T
A
= T
MIN
to T
MAX
J/K/A/B
MAX
MIN
0
120
120
S/T
MAX
ns
ns
ns
ns
ns
ns
ns
ns
UNITS
Note 5:
Timing specifications are sample tested at +25°C to ensure compliance. All input control signals are specified with
t
r
= t
f
= 20ns (10% to 90% of +5V) and timed from a voltage level of 1.6V.
Note 6:
t
3
and t
6
are measured with the load circuits of Figure 1 and defined as the time required for an output to cross 0.8V or 2.4V.
Note 7:
t
7
is defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2.
______________________________________________________________Pin Description
PIN
DIP/SO
1
2
PLCC
2
3
NAME
CS
RD
FUNCTION
Chip Select Input.
CS
must be low for the device to be selected or to recognize the
RD
input.
Read Input.
RD
must be low to access data.
RD
is also used to start conversions. See the
Microprocessor Interface
section.
3
4
TP
Test Point. Connect to V
DD
.
(MX7575)
MODE
Mode Input. MODE = low puts the ADC into its asynchronous conversion mode. MODE has to be
(MX7576) tied high for the synchronous conversion mode and the ROM interface mode.
BUSY
CLK
D7
D6, D5
DGND
D4–D1
D0
AGND
AIN
REF
V
DD
N.C.
BUSY
Output.
BUSY
going low indicates the start of a conversion.
BUSY
going high indicates the
end of a conversion.
External Clock Input/Internal Oscillator Pin for frequency setting RC components.
Three-State Data Output, bit 7 (MSB)
Three-State Data Outputs, bits 6 and 5
Digital Ground
Three-State Data Outputs, bits 4–1
Three-State Data Output, bit 0 (LSB)
Analog Ground
Analog Input. 0V to 2V
REF
input range.
Reference Input. +1.23V nominal.
Power-Supply Voltage. +5V nominal.
No Connect
4
5
6
7, 8
9
10–13
14
15
16
17
18
—
5
6
7
8, 9
10
12–15
16
17
18
19
20
1, 11
4
_______________________________________________________________________________________
CMOS, µP-Compatible, 5µs/10µs, 8-Bit ADCs
MX7575/MX7576
+5V
3k
D_
3k
DGND
a) HIGH-Z TO V
OH
NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS
100pF
DGND
b) HIGH-Z TO V
OL
D_
100pF
D_
3k
DGND
a) V
OH
TO HIGH-Z
NOTE: D_ REPRESENTS ANY OF THE DATA OUTPUTS
10pF
DGND
b) V
OL
TO HIGH-Z
D_
10pF
+5V
3k
Figure 1. Load Circuits for Data-Access Time Test
Figure 2. Load Circuits for Data-Hold Time Test
_______________Detailed Description
Converter Operation
The MX7575 and MX7576 use the successive-approxi-
mation technique to convert an unknown analog input
voltage to an 8-bit digital output code (see
Functional
Diagrams).
The MX7575 samples the input voltage on
an internal capacitor once (at the beginning of the con-
version), while the MX7576 samples the input signal
eight times during the conversion (see
MX7575
Track/Hold
and
MX7576 Analog Input
sections). The
internal DAC is initially set to half scale, and the com-
parator determines whether the input signal is larger
than or smaller than half scale. If it is larger than half
scale, the DAC MSB is kept. But if it is smaller, the MSB
is dropped. At the end of each comparison phase, the
SAR (successive-approximation register) stores the
results of the previous decision and determines the
next trial bit. This information is then loaded into the
DAC after each decision. As the conversion proceeds,
the analog input is approximated more closely by com-
paring it to the combination of the previous DAC bits
and a new DAC trial bit. After eight comparison cycles,
the eight bits stored in the SAR are latched into the out-
put latches. At the end of the conversion, the
BUSY
sig-
nal goes high, and the data in the output latches is
ready for microprocessor (µP) access. Furthermore, the
DAC is reset to half scale in preparation for the next
conversion.
are performed. In the slow-memory interface mode,
CS
and
RD
are taken low to start a conversion and they
remain low until the conversion ends, at which time the
conversion result is latched. This mode is designed for
µPs that can be forced into a wait state. In the ROM
interface mode, however, the µP is not forced into a wait
state. A conversion is started by taking
CS
and
RD
low,
and data from the previous conversion is read. At the
end of the most recent conversion, the µP executes a
read instruction and starts another conversion.
For the MX7575, TP should be hard-wired to V
DD
to
ensure proper operation of the device. Spurious signals
may occur on TP, or excessive currents may be drawn
from V
DD
if TP is left open or tied to a voltage other than
V
DD
.
Microprocessor Interface
The
CS
and
RD
logic inputs are used to initiate conver-
sions and to access data from the devices. The MX7575
and MX7576 have two common interface modes: slow-
memory interface mode and ROM interface mode. In
addition, the MX7576 has an asynchronous conversion
mode (MODE pin = low) where continuous conversions
Slow-Memory Mode
Figure 3 shows the timing diagram for slow-memory
interface mode. This is used with µPs that have a wait-
state capability of at least 10µs (such as the 8085A),
where a read instruction is extended to accommodate
slow-memory devices. A conversion is started by exe-
cuting a memory read to the device (taking
CS
and
RD
low). The
BUSY
signal (which is connected to the µP
READY input) then goes low and forces the µP into a
wait state. The MX7575 track/hold, which had been
tracking the analog input signal, holds the signal on the
third falling clock edge after
RD
goes low (Figure 12).
The MX7576, however, samples the analog input eight
times during a conversion (once before each compara-
tor decision). At the end of the conversion,
BUSY
returns high, the output latches and buffers are updat-
ed with the new conversion result, and the µP com-
pletes the memory read by acquiring this new data.
The fast conversion time of the MX7575/MX7576
ensures that the µP is not forced into a wait state for an
excessive amount of time. Faster versions of many µPs,
5
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