ZL49030DDF1 datasheet, PDF - EEWORLD Datasheet

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ZL49030DDF1: DescriptionTELECOM, DTMF SIGNALING CIRCUIT, PDIP8; CategoryTopical application Wireless rf/communication; File Size397KB，15 Pages; ManufacturerZarlink Semiconductor (Microsemi); Websitehttp://www.zarlink.com/

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ZL49030DDF1 Overview

TELECOM, DTMF SIGNALING CIRCUIT, PDIP8

ZL49030DDF1 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	8
Minimum operating temperature	-40 Cel
Maximum operating temperature	85 Cel
Processing package description	LEAD FREE, PLASTIC, MS-001BA, DIP-8
state	Transferred
Communication type	DTMF SIGNALING CIRCUIT
jesd_30_code	R-PDIP-T8
jesd_609_code	e3
Packaging Materials	PLASTIC/EPOXY
ckage_code	DIP
ckage_equivalence_code	DIP8,.3
packaging shape	RECTANGULAR
Package Size	IN-LINE
wer_supplies__v_	5
qualification_status	COMMERCIAL
seated_height_max	5.33 mm
sub_category	Telecom Signaling Circuits
Maximum supply voltage	0.0080 mA
Rated supply voltage	5 V
surface mount	NO
Temperature level	INDUSTRIAL
terminal coating	MATTE TIN
Terminal form	THROUGH-HOLE
Terminal spacing	2.54 mm
Terminal location	DUAL
length	9.59 mm
width	7.62 mm

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ZL49010/11, ZL49020/21, ZL49030/31

Wide Dynamic Range DTMF Receiver

Data Sheet

Features

•

Wide dynamic range (50 dB) DTMF Receiver

Call progress (CP) detection via cadence

indication

4-bit synchronous serial data output

Software controlled guard time for ZL490x0

Internal guard time circuitry for ZL490x1

Powerdown option (ZL4901x & ZL4903x)

3.579 MHz crystal or ceramic resonator (ZL4903x

and ZL4902x)

External clock input (ZL4901x)

Guarantees non-detection of spurious tones

Ordering Information

ZL49010/11DAA

ZL49020/21DAA

ZL49030/31DCA

ZL49030/31DCB

ZL49030/31DDA

ZL49030/31DDB

ZL49010/11DAA1

ZL49020/21DAA1

ZL49030/31DCE1

ZL49030/31DCF1

Tubes

Tape & Reel

Tubes

Tape & Reel

Tubes

Tubes, Bake & Drypack

Tape & Reel,

Bake & Drypack

ZL49030/31DDE1 20 Pin SSOP* Tubes, Bake & Drypack

ZL49030/31DDF1 20 Pin SSOP* Tubes, Bake & Drypack

*Pb Free Matte Tin

-40°C to +85°C

8 Pin PDIP

18 Pin SOIC

20 Pin SSOP

8 Pin PDIP*

18 Pin SOIC*

February 2007

Applications

•

Integrated telephone answering machine

End-to-end signalling

Fax Machines

Description

The ZL490xx is a family of high performance DTMF

receivers which decode all 16 tone pairs into a 4-bit

binary code. These devices incorporate an AGC for

wide dynamic range and are suitable for end-to-end

signalling. The ZL490x0 provides an early steering

(ESt) logic output to indicate the detection of a DTMF

signal and requires external software guard time to

validate the DTMF digit. The ZL490x1, with preset

internal guard times, uses a delay steering (DStD)

logic output to indicate the detection of a valid DTMF

digit. The 4-bit DTMF binary digit can be clocked out

synchronously at the serial data (SD) output. The SD

pin is multiplexed with call progress detector output. In

the presence of supervisory tones, the call progress

detector circuit indicates the cadence (i.e., envelope)

of the tone burst. The cadence information can then be

processed by an external microcontroller to identify

PWDN

VDD

VSS

Voltage

Bias Circuit

Steering

Circuit

High

Group

Filter

Anti-

alias

Filter

Dial

Tone

Filter

Low

Group

Filter

Digital

Detector

Algorithm

Code

Converter

and

Latch

Digital

Guard

Time

Parallel to

Serial

Converter

& Latch

ESt

DStD

ACK

AGC

Mux

OSC2

OSC1

(CLK)

Oscillator

and

Clock

Circuit

To All Chip Clocks

Energy

Detection

ZL49010/1 and ZL49030/1 only.

ZL49020/1 and ZL49030/1 only.

ZL490x1 only.

Figure 1 - Functional Block Diagram

Zarlink Semiconductor Inc.

Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

ZL49010/11, ZL49020/21, ZL49030/31

Functional Description

Data Sheet

The ZL490xxs are high performance and low power consumption DTMF receivers. These devices provide wide

dynamic range DTMF detection and a serial decoded data output. These devices also incorporate an energy

detection circuit. An input voiceband signal is applied to the devices via a series decoupling capacitor. Following the

unity gain buffering, the signal enters the AGC circuit followed by an anti-aliasing filter. The bandlimited output is

routed to a dial tone filter stage and to the input of the energy detection circuit. A bandsplit filter is then used to

separate the input DTMF signal into high and low group tones. The high group and low group tones are then

verified and decoded by the internal frequency counting and DTMF detection circuitry. Following the detection

stage, the valid DTMF digit is translated to a 4-bit binary code (via an internal look-up ROM). Data bits can then be

shifted out serially by applying external clock pulses.

Automatic Gain Control (AGC) Circuit

As the device operates on a single power supply, the input signal is biased internally at approximately VDD/2. With

large input signal amplitude (between 0 and approximately -30 dBm for each tone of the composite signal), the

AGC is activated to prevent the input signal from being clipped. At low input level, the AGC remains inactive and the

input signal is passed directly to the hardware DTMF detection algorithm and to the energy detection circuit.

Filter and Decoder Section

The signal entering the DTMF detection circuitry is filtered by a notch filter at 350 and 440 Hz for dial tone rejection.

The composite dual-tone signal is further split into its individual high and low frequency components by two 6

order switched capacitor bandpass filters. The high group and low group tones are then smoothed by separate

output filters and squared by high gain limiting comparators. The resulting squarewave signals are applied to a

digital detection circuit where an averaging algorithm is employed to determine the valid DTMF signal. For

ZL490x0, upon recognition of a valid frequency from each tone group, the early steering (ESt) output will go high,

indicating that a DTMF tone has been detected. Any subsequent loss of DTMF signal condition will cause the ESt

pin to go low. For ZL490x1, an internal delayed steering counter validates the early steering signal after a

predetermined guard time which requires no external components. The delayed steering (DStD) will go high only

when the validation period has elapsed. Once the DStD output is high, the subsequent loss of early steering signal

due to DTMF signal dropout will activate the internal counter for a validation of tone absent guard time. The DStD

output will go low only after this validation period.

Energy Detection

The output signal from the AGC circuit is also applied to the energy detection circuit. The detection circuit consists

of a threshold comparator and an active integrator. When the signal level is above the threshold of the internal

comparator (-35 dBm), the energy detector produces an energy present indication on the SD output. The integrator

ensure the SD output will remain at high even though the input signal is changing. When the input signal is

removed, the SD output will go low following the integrator decay time. Short decay time enables the signal

envelope (or cadence) to be generated at the SD output. An external microcontroller can monitor this output for

specific call progress signals. Since presence of speech and DTMF signals (above the threshold limit) can cause

the SD output to toggle, both ESt (DStD) and SD outputs should be monitored to ensure correct signal identification.

As the energy detector is multiplexed with the digital serial data output at the SD pin, the detector output is selected

at all times except during the time between the rising edge of the first pulse and the falling edge of the fourth pulse

applied at the ACK pin.

Serial Data (SD) Output

When a valid DTMF signal burst is present, ESt or DStD will go high. The application of four clock pulses on the

ACK pin will provide a 4-bit serial binary code representing the decoded DTMF digit on the SD pin output. The rising

edge of the first pulse applied on the ACK pin latches and shifts the least significant bit of the decoded digit on the

SD pin. The next three pulses on ACK pin will shift the remaining latched bits in a serial format (see Figure 5). If less

than four pulses are applied to the ACK pin, new data cannot be latched even though ESt/DStD can be valid. Clock

pulses should be applied to clock out any remaining data bits to resume normal operation. Any transitions in excess

Zarlink Semiconductor Inc.

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