NLV74HC4046ADR2G datasheet, PDF

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NLV74HC4046ADR2G: DescriptionIC PHASE LOCKED LOOP 16SOIC; Categorysemiconductor Analog mixed-signal IC; File Size164KB，18 Pages; ManufacturerON Semiconductor; Websitehttp://www.onsemi.cn; Environmental Compliance

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NLV74HC4046ADR2G Overview

IC PHASE LOCKED LOOP 16SOIC

NLV74HC4046ADR2G Parametric

Parameter Name	Attribute value
PLL	yes
enter	CMOS，TTL
output	CMOS，TTL
Number of circuits	1
Ratio - Input:Output	2：3
Differential - Input:Output	No/Yes
Frequency - maximum	13MHz
Frequency divider/multiplier	None/None
Voltage - Power	2 V ~ 6 V
Operating temperature	-55°C ~ 125°C
Installation type	surface mount
Package/casing	16-SOIC (0.154", 3.90mm wide)
Supplier device packaging	16-SOIC

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MC74HC4046A

Phase−Locked Loop

High−Performance Silicon−Gate CMOS

The MC74HC4046A is similar in function to the MC14046 Metal

gate CMOS device. The device inputs are compatible with standard

CMOS outputs; with pullup resistors, they are compatible with

LSTTL outputs.

The HC4046A phase−locked loop contains three phase

comparators, a voltage−controlled oscillator (VCO) and unity gain

op−amp DEM

OUT

. The comparators have two common signal inputs,

COMP

, and SIG

. Input SIG

and COMP

can be used directly

coupled to large voltage signals, or indirectly coupled (with a series

capacitor to small voltage signals). The self−bias circuit adjusts small

voltage signals in the linear region of the amplifier. Phase comparator

1 (an exclusive OR gate) provides a digital error signal PC1

OUT

and

maintains 90 degrees phase shift at the center frequency between

SIG

and COMP

signals (both at 50% duty cycle). Phase

comparator 2 (with leading−edge sensing logic) provides digital error

signals PC2

OUT

and PCP

OUT

and maintains a 0 degree phase shift

between SIG

and COMP

signals (duty cycle is immaterial). The

linear VCO produces an output signal VCO

OUT

whose frequency is

determined by the voltage of input VCO

signal and the capacitor

and resistors connected to pins C1A, C1B, R1 and R2. The unity gain

op−amp output DEM

OUT

with an external resistor is used where the

VCO

signal is needed but no loading can be tolerated. The inhibit

input, when high, disables the VCO and all op−amps to minimize

standby power consumption.

Applications include FM and FSK modulation and demodulation,

frequency synthesis and multiplication, frequency discrimination,

tone decoding, data synchronization and conditioning,

voltage−to−frequency conversion and motor speed control.

Features

http://onsemi.com

MARKING

DIAGRAMS

PDIP−16

N SUFFIX

CASE 648

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16

DT SUFFIX

CASE 948F

SOEIAJ−16

F SUFFIX

CASE 966

74HC4046A

ALYWG

HC40

46A

ALYWG

HC4046AG

AWLYWW

MC74HC4046AN

AWLYYWWG

•

Output Drive Capability: 10 LSTTL Loads

Low Power Consumption Characteristic of CMOS Devices

Operating Speeds Similar to LSTTL

Wide Operating Voltage Range: 3.0 to 6.0 V

Low Input Current: 1.0

Maximum (except SIG

and COMP

)

In Compliance with the Requirements Defined by JEDEC Standard

No. 7A

Low Quiescent Current: 80

Maximum (VCO disabled)

High Noise Immunity Characteristic of CMOS Devices

Diode Protection on all Inputs

Chip Complexity: 279 FETs or 70 Equivalent Gates

Pb−Free Packages are Available*

= Assembly Location

L, WL

= Wafer Lot

Y, YY

= Year

W, WW = Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2005

June, 2005 − Rev. 8

Publication Order Number:

MC74HC4046A/D

NLV74HC4046ADR2G Related Products

	NLV74HC4046ADR2G	MC74HC4046A_05	MC74HC4046A
Description	IC PHASE LOCKED LOOP 16SOIC	PHASE LOCKED LOOP, PDIP16	PHASE LOCKED LOOP, PDIP16
Number of functions	-	1	1
Number of terminals	-	16	16
Maximum operating temperature	-	125 Cel	125 Cel
Minimum operating temperature	-	-55 Cel	-55 Cel
Maximum supply/operating voltage	-	6 V	6 V
Minimum supply/operating voltage	-	3 V	3 V
Rated supply voltage	-	5 V	5 V
Processing package description	-	Plastic, DIP-16	Plastic, DIP-16
state	-	TRANSFERRED	TRANSFERRED
Craftsmanship	-	CMOS	CMOS
packaging shape	-	Rectangle	Rectangle
Package Size	-	IN-line	IN-line
Terminal form	-	THROUGH-hole	THROUGH-hole
Terminal spacing	-	2.54 mm	2.54 mm
Terminal location	-	pair	pair
Packaging Materials	-	Plastic/Epoxy	Plastic/Epoxy
Temperature level	-	MILITARY	MILITARY
Analog IC other types	-	phase locked loop	phase locked loop

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