531DA200M000DG datasheet, PDF - EEWORLD Datasheet

Datasheet> All Categories > Passive components> oscillator> 531DA200M000DG

531DA200M000DG: DescriptionSINGLE FREQUENCY XO, OE PIN 1; CategoryPassive components oscillator; File Size450KB，12 Pages; ManufacturerSilicon Laboratories Inc; Environmental Compliance

Download Datasheet Parametric View All

531DA200M000DG Online Shopping

Suppliers	Part Number	Price	MOQ	In stock
	531DA200M000DG	-	-	View	Buy Now

531DA200M000DG Overview

SINGLE FREQUENCY XO, OE PIN 1

531DA200M000DG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Silicon Laboratories Inc
package instruction	ROHS COMPLIANT, SMD, 6 PIN
Reach Compliance Code	compliant
Other features	TRAY
maximum descent time	0.35 ns
Frequency Adjustment - Mechanical	NO
frequency stability	50%
JESD-609 code	e4
Manufacturer's serial number	531
Installation features	SURFACE MOUNT
Nominal operating frequency	200 MHz
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Oscillator type	CMOS/TTL
physical size	7.0mm x 5.0mm x 1.85mm
longest rise time	0.35 ns
Maximum supply voltage	3.63 V
Minimum supply voltage	2.97 V
Nominal supply voltage	3.3 V
surface mount	YES
maximum symmetry	55/45 %
Terminal surface	Nickel/Gold (Ni/Au)
Base Number Matches	1

Preview

Download Datasheet

View All

S i 5 3 0 / 5 31

EVISION

R YS TA L

SCILLATOR

(XO) (10 M H

Features

Available with any-rate output



frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz



3rd generation DSPLL

with superior



jitter performance



3x better frequency stability than



SAW-based oscillators



1.4 GH

)

Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout



Pb-free/RoHS-compliant

Si5602

Ordering Information:

See page 7.

Applications

SONET/SDH



Networking



SD/HD video



Test and measurement



Clock and data recovery



FPGA/ASIC clock generation



Pin Assignments:

See page 6.

(Top View)

GND

Description

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

CLK–

CLK+

Si530 (LVDS/LVPECL/CML)

GND

Functional Block Diagram

CLK– CLK+

CLK

Si530 (CMOS)

Fixed

Frequency

Any-rate

10–1400 MHz

DSPLL

Clock

Synthesis

GND

CLK–

CLK+

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.5 6/18

Si530/531

Recommended Resources

Thyristor AC switch circuit 6b

Setting up of pumping pipes

Midea EF-836T Lucky Fan circuit diagram

Charge pump circuit principle no-load circuit diagram

Computer wireless data transceiver circuit diagram

810 computer motherboard circuit diagram_08

Free review: HuaDa M4 core HC32F460 board, #all serial communication ports, GPIO can be freely mapped# Is it fresh?: "All serial communication (UART, I2C, SPI, CAN, I2S) ports can be freely mapped to 64 GPIOs, making PCB board manufacturing easy" This may not be a new feature in the field of single-chip microcompute...; EEWORLD社区 Domestic Chip Exchange

Playing with Zynq Serial 13 - Using GIT for project backup and version management 5: 2.5 View old version filesUse the Show Log command to view the local version information, select the old version you want to view, such as ver1 here , right-click and select the command Reset “master”...; ove学习使我快乐 FPGA/CPLD

Help: mspf169 operation P1.4 port program runs out of control: [backcolor=rgb(239, 245, 249)]I am using 5310's P1.4 to control the MOS tube switch, but it always runs out of control when executing P1DIR |= BIT4. What is going on? Thank you! [/backcolor]...; fish001 Microcontroller MCU

Analog Electronics: Answer key to analog electronics textbook...; liubowd Analog electronics

STM32 single timer realizes 4-way signal capture: This program uses the registers of stm32 to perform a four-way capture frequency experiment on a single timer. The relevant parameters can be well applied to practice...; ITPOWER stm32/stm8

FRAM storage problem of 430FR5969: Because AD sampling requires the definition of a large array, I used the following CMD file! But after using it, I found that the data written to the FRAM2 address could not be stored! Please help! Th...; yingonly2016 Microcontroller MCU

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components