Data Sheet
FEATURES
Low Power HDMI to LVDS Display Bridge
ADV7613
Dedicated, flexible audio output port
Dolby® TrueHD DTS-HD Master Audio™
General
Internal EDID RAM
Integrated consumer electronics control (CEC) controller
Standard identification (STDI) circuit
Any to any, 3 × 3 color space conversion (CSC) matrix
100-ball, 9 mm × 9 mm CSP_BGA package
Qualified for automotive applications
Single-input HDMI receiver with dual channel LVDS
transmitter outputs
HDMI receiver support
148.5 MHz maximum TMDS clock frequency
High-bandwidth Digital Content Protection (HDCP) 1.4
support with internal HDCP keys
Adaptive HDMI equalizer
5 V detect and hot plug assert for HDMI port
Extended colorimetry, including sYCC601, Adobe RGB,
Adobe YCC 601, xvYCC extended gamut color
LVDS transmitters
Dual channel 24-bit OpenLDI interface
Supports 6-bit and 8-bit nonbalanced OpenLDI or 8-bit
video electronics standards association (VESA) formats
Audio support including high bit rate (HBR) and Direct
Stream Digital (DSD)
S/PDIF (IEC 60958-compatible) digital audio support
APPLICATIONS
Projectors
Automotive infotainment headunits
Automotive infotainment displays
Digital signage
FUNCTIONAL BLOCK DIAGRAM
REFERENCE
CLOCK
DIGITAL
CLOCK
SYNTHESIS
PACKET
INFOFRAME
MEMORY
AUDIO
PACKET
PROCESSOR
AUDIO
INTERFACE
AUDIO
OUTPUT
INT
HDMI
CABLE
EQUALIZER
HDMI
PROCESSOR
COMPONENT
PROCESSOR
DDC
EDID
CONTROL
HDCP
KEYS
HOST I/F
CONFIGURATION
AND CONTROL
OpenLDI
ENCODER
LVDS Tx
LVDS Tx
DUAL
LVDS Tx
OUTPUT
I
2
C SLAVE
13676-001
RESET
Figure 1.
Rev. C
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ADV7613
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Detailed Functional Block Diagram .......................................... 3
Specifications..................................................................................... 4
Electrical Characteristics ............................................................. 4
LVDS Transmitter (OpenLDI Mapping) ................................... 5
Data and I
2
C Timing Characteristics ......................................... 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Data Sheet
Power Supply Recommendations ................................................. 11
Power-Up Sequence ................................................................... 11
Power-Down Sequence.............................................................. 11
Theory of Operation ...................................................................... 12
HDMI Receiver........................................................................... 12
HDCP Repeater Functionality ................................................. 12
Component Processor (CP) ...................................................... 12
LVDS Transmitter Features ....................................................... 12
I
2
C Interface ................................................................................ 12
Other Features ............................................................................ 12
Audio Output Data .................................................................... 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 13
Automotive Products ................................................................. 13
REVISION HISTORY
9/2018—Rev.
B to Rev. C
Changes to Ordering Guide .......................................................... 13
5/2017—Rev. A to Rev. B
Changes to LVDS Transmitter Features Section ........................ 12
Changes to Ordering Guide .......................................................... 13
12/2015—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 13
10/2015—Revision 0: Initial Version
Rev. C | Page 2 of 13
Data Sheet
GENERAL DESCRIPTION
The
ADV7613
is a high quality, low power, single-input HDMI
to LVDS display bridge. It incorporates an HDMI capable
receiver that supports up to 1080p, 60 Hz.
The HDMI port has dedicated 5 V detect and hot plug assert
pins. The HDMI receiver also includes an integrated equalizer
that ensures the robust operation of the interface with long
cables.
The
ADV7613
has an audio output port for the audio data
extracted from the HDMI stream. HDMI audio formats include
super audio CD (SACD) via Direct Stream Digital® (DSD) and
HBR. The HDMI receiver has an advanced mute controller that
prevents audible extraneous noise in the audio output.
The
ADV7613
contains a component processor (CP) that
processes the video signals from the HDMI receiver. It provides
features such as contrast, brightness and saturation adjustments,
ADV7613
STDI detection block, free run, and synchronization alignment
controls.
The LVDS encoder can package data into 6-bit or 8-bit non-dc
balanced OpenLDI mapping or 8-bit VESA mapping. The
ADV7613
can output 24-bit OpenLDI data via dual-channel
LVDS transmitters, up to a maximum resolution of 1080p,
60 Hz received at the input. The maximum output clock
supported by a single LVDS output port is 92 MHz.
The
ADV7613
is offered in an automotive grade and a con-
sumer grade. The operating temperature range is −40°C to
+85°C.
Fabricated in an advanced CMOS process, the
ADV7613
is
provided in a 9 mm × 9 mm, 100-ball CSP_BGA, RoHS-
compliant package.
DETAILED FUNCTIONAL BLOCK DIAGRAM
ADV7613
XTALP
XTALN
SCL
SDA
CS
CEC
CEC
CONTROLLER
DATA
PREPROCESSOR
AND COLOR SPACE
CONVERSION
CONTROL
INTERFACE
I
2
C
COMPONENT
PROCESSOR
A
B
C
BACK‐END
COLOR SPACE
CONVERSION
LVDS FORMATTER
DPLL
LTX1_0+
LTX1_0–
LTX1_1+
LTX1_1–
LTX1_2+
LTX1_2–
LTX1_3+
LTX1_3–
LTX1_C+
LTX1_C–
LTX2_0+
LTX2_0–
LTX2_1+
LTX2_1–
LTX2_2+
LTX2_2–
LTX2_3+
LTX2_3–
LTX2_C+
LTX2_C–
INT
AP0
RXA_5V
HPA_A
5V DETECT AND
HPD CONTROLLER
HDMI
PROCESSOR
DDCA_SDA
DDCA_SCL
EDID REPEATER
CONTROLLER
HDCP
KEYS
INTERRUPT
CONTROLLER
AUDIO OUTPUT
FORMATTER
PACKET/INFOFRAME
MEMORY
AP1
AP2
AP3
AP4
AP5
SCLK
MCLKOUT
13676-002
RXA_C±
PLL
RXA_0±
RXA_1±
RXA_2±
EQUALIZER
SAMPLER
HDCP
ENGINE
PACKET
PROCESSOR
AUDIO
PROCESSOR
Figure 2. Detailed Functional Block Diagram
Rev. C | Page 3 of 13
ADV7613
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Data Sheet
DVDD = 1.71 V to 1.89 V, DVDDIO = 3.135 V to 3.465 V, PVDD = 1.71 V to 1.89 V, TVDD = 3.135 V to 3.465 V, CVDD = 1.71 V to
1.89 V, LTX_VDD = 1.71 V to 1.89 V. T
MIN
to T
MAX
= −40°C to +85°C, unless otherwise noted.
Table 1.
Parameter
DIGITAL INPUTS
Input High Voltage
Input Low Voltage
Input Current
Symbol
V
IH
V
IL
I
IN
Test Conditions/Comments
XTALN and XTALP pins
Other digital inputs
XTALN and XTALP pins
Other digital inputs
CS pin
XTALN and XTALP pins
Other digital inputs
DDCA_SCL, DDCA_SDA
V
IH
V
IL
I
IN
I
IN
V
OH
V
OL
I
LEAK
2.6
−80
−100
2.4
HPA_A
3
Min
1.2
2
Typ
Max
Unit
V
V
V
V
µA
µA
µA
pF
V
V
µA
µA
V
V
µA
µA
pF
V
V
V
V
V
V
−60
±15
±10
0.4
0.8
+60
Input Capacitance
1
DIGITAL INPUTS (5 V TOLERANT)
2
Input High Voltage
Input Low Voltage
Input Current
Input Leakage Current
DIGITAL OUTPUTS
Output High Voltage
Output Low Voltage
High Impedance Leakage
Current
Output Capacitance
POWER REQUIREMENTS
Termination Power Supply
Digital Input/Output (I/O)
Power Supply
Digital Core Power Supply
Phase-Locked Loop (PLL)
Power Supply
Comparator Power Supply
LVDS Power Supply
CURRENT CONSUMPTION
4
Configuration 1
4
C
IN
10
RXA_5V
0.8
+80
+100
−100
−10
0.4
+100
+10
20
3.3
3.3
1.8
1.8
1.8
1.8
3.465
3.465
1.89
1.89
1.89
1.89
Other digital outputs
C
OUT
TVDD
DVDDIO
DVDD
PVDD
CVDD
LTX_VDD
Pseudorandom test pattern; 1360 × 768p at 60 Hz input
resolution; 85 MHz pixel clock; 25°C operating temperature;
DVDD, PVDD, CVDD, and LTX_DVDD = 1.8 V; DVDDIO and
TVDD = 3.3 V; LVDS Port 2 used
I
TVDD
I
DVDDIO
I
DVDD
I
PVDD
I
CVDD
I
LTX_VDD
Checker one-dot × one-dot test pattern; 1920 × 720p at
60 Hz input resolution; 92 MHz pixel clock; 25°C operating
temperature; DVDD, PVDD, CVDD, and LTX_DVDD = 1.8 V;
DVDDIO and TVDD = 3.3 V; LVDS Port 2 used
I
TVDD
I
DVDDIO
I
DVDD
Rev. C | Page 4 of 13
3.135
3.135
1.71
1.71
1.71
1.71
Termination Power Supply
Digital I/O Power Supply
Digital Core Power Supply
PLL Power Supply
Comparator Power Supply
LVDS Power Supply
Configuration 2
50
6
68
29
65
45
mA
mA
mA
mA
mA
mA
Termination Power Supply
Digital I/O Power Supply
Digital Core Power Supply
58
6
102
mA
mA
mA
Data Sheet
Parameter
PLL Power Supply
Comparator Power Supply
LVDS Power Supply
Configuration 3
Symbol
I
PVDD
I
CVDD
I
LTX_VDD
Test Conditions/Comments
Min
Typ
29
66
43
ADV7613
Max
Unit
mA
mA
mA
Pseudorandom test pattern; 1920 × 1080p at 60 Hz input
resolution; 148.5 MHz pixel clock; 85°C operating temperature;
DVDD, PVDD, CVDD, and LTX_DVDD = 1.89 V; DVDDIO and
TVDD = 3.465 V; LVDS Port 1 and LVDS Port 2 used
I
TVDD
I
DVDDIO
I
DVDD
I
PVDD
I
CVDD
I
LTX_VDD
I
TVDD_PD
I
DVDDIO_PD
I
DVDD_PD
I
PVDD_PD
I
CVDD_PD
I
LTX_VDD_PD
327
387
102
223
74
323
70
15
147
44
96
88
mA
mA
mA
mA
mA
mA
µA
µA
µA
µA
µA
µA
Termination Power Supply
Digital I/O Power Supply
Digital Core Power Supply
PLL Power Supply
Comparator Power Supply
LVDS Power Supply
POWER-DOWN CURRENT⁴
Terminator Power Supply
Digital I/O Power Supply
Digital Core Power Supply
PLL Power Supply
Comparator Power Supply
LVDS Power Supply
1
2
Data characterized by evaluation.
The following pins are 5 V tolerant inputs: DDCA_SCL, DDCA_SDA, and RXA_5V.
3
The HPA_A pin is a 5 V tolerant output.
4
Data characterized by evaluation.
LVDS TRANSMITTER (OpenLDI MAPPING)
Table 2.
Parameter
OpenLDI OUTPUTS
1
Differential Output Voltage
Offset Output Voltage
Change in V
OD
Mismatch
Change in V
OS
Mismatch
OpenLDI TRANSMITTER
2
OpenLDI Output Rise Time
OpenLDI Output Fall Time
1
2
Symbol
V
OD
V
OS
Min
247
1.125
Typ
350
1.2
Max
454
1.375
50
50
0.3 × UI
0.3 × UI
Unit
mV
V
mV
mV
ps
ps
t
R
t
F
0.21 × UI
0.21 × UI
Measurement performed using a 100 Ω termination resistor.
Data characterized by evaluation, using a 100 Ω source termination resistor. UI is unit interval, that is, the bit width.
DATA AND I
2
C TIMING CHARACTERISTICS
Table 3.
Parameter
CLOCK AND CRYSTAL
Crystal (XTAL) Frequency
XTAL Frequency Stability
Input Clock Range (TMDS)
OpenLDI Output Clock Range
I
2
C PORTS
SCL Frequency
SCL Minimum Pulse Width High
SCL Minimum Pulse Width Low
Start Condition Hold Time
Symbol
Min
Typ
28.63636
25
25
±50
148.5
92
400
t
1
t
2
t
3
Rev. C | Page 5 of 13
Max
Unit
MHz
ppm
MHz
MHz
kHz
ns
µs
ns
600
1.3
600
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