ZL30623
Dual-Channel Any Frequency Timing Card
PLL with Ultra Low Jitter
Product Brief
September 2015
Features
Two Independent Channels
Low-Bandwidth DPLL Per Channel
ITU-T G.813/G.8262 compliance (options 1 & 2)
Programmable bandwidth, 0.1Hz to 500Hz
Attenuates jitter up to several UI
Freerun or holdover on loss of all inputs
Hitless reference switching
High-resolution holdover averaging
Digitally controlled phase adjustment
Three Input Clocks Per Channel
Three inputs, two differential/CMOS, one CMOS
Any input frequency from 8kHz to 1250MHz
(8kHz to 300MHz for CMOS)
Per-input activity and frequency monitoring
Automatic or manual reference switching
Low-Jitter Fractional-N APLL and 3 Outputs Per
Channel
Any output frequency from <1Hz to 1035MHz
High-resolution fractional frequency conversion
with 0ppm error
Encapsulated design requires no external
VCXO or loop filter components
Output jitter as low as 0.25ps RMS (12kHz-
20MHz integration band)
Each Channel:
IC1P, IC1N
IC2P, IC2N
IC3P/GPIO3
Ordering Information
ZL30623LFG7
ZL30623LFF7
64 Pin LGA
64 Pin LGA
Ni Au
Package size: 5 x 10 mm
-40
C to +85
C
Trays
Tape and Reel
Outputs are CML or 2xCMOS, can interface to
LVDS, LVPECL, HSTL, SSTL and HCS
In 2xCMOS mode, the P and N pins can be
different frequencies (e.g. 125MHz and 25MHz)
Per-output supply pin with CMOS output
voltages from 1.5V to 3.3V
Precise output alignment circuitry and per-
output phase adjustment
Per-output enable/disable and glitchless
start/stop (stop high or low)
General Features
Automatic self-configuration at power-up from
internal EEPROM; up to four configurations
pin-selectable
Numerically controlled oscillator mode
Input-to-output alignment with external feedback
SPI or I C processor Interface
2
Easy-to-use evaluation software
Applications
Telecom timing cards for SONET/SDH, SyncE,
wireless base stations and other systems
HSDIV1
HSDIV2
HSDIV3
Input Block
Divider,
Monitor,
Selector
Hitless Switching,
Jitter Filtering,
Holdover
DPLL
APLL
~3.7 to 4.2GHz,
Fractional-N
HSDIV1
DIV1
DIV2
HSDIV2
DIV3
OC1P, OC1N
VDDO1
OC2P, OC2N
VDDO2
OC3P, OC3N
VDDO3
TCXO
XA
XB
xtal
driver
×2
(SPI or I2C Serial)
and HW Control and Status Pins
Microprocessor Port
AC0/GPIO0
AC1/GPIO1
TEST/GPIO2
IC3P/GPIO3
RSTN
IF0/CSN
SCL/SCLK
Figure 1 - Functional Block Diagram
1
Microsemi Corporation
Copyright 2015. Microsemi Corporation. All Rights Reserved.
SDA/MOSI
IF1/MISO
ZL30623
1. Application Examples
Product Brief
Processor
SPI
freq ctrl
TCXO
Channel A
(NCO mode)
25MHz CMOS
1PPS CMOS
2x 156.25MHz differential
125MHz CMOS
25MHz CMOS
Input clock monitoring, hitless switching, frequency conversion,
and jitter attenuation if needed.
From PHYs
and other
sources
Channel B
19.44M,
25M, etc.
Figure 2 – Telecom Timing Card Application
2. Detailed Features
2.1
Input Block Features
Three input clocks per channel, two differential or single-ended, one single-ended
Input clocks can be any frequency from 8kHz up to 1250MHz (differential) or 300MHz (single-ended)
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN, wireless
Inputs constantly monitored by programmable activity monitors and frequency monitors
Fast activity monitor can disqualify the input after a few missing clock cycles
Frequency measurement and monitoring with 1ppm resolution and accept/reject hysteresis
Optional input clock invalidation on GPIO assertion to react to LOS signals from PHYs
One DPLL per channel
Very high-resolution DPLL architecture
State machine automatically transitions between tracking and freerun/holdover states
Revertive or nonrevertive reference selection algorithm
Programmable bandwidth from 0.1Hz to 500Hz
Less than 0.1dB gain peaking
Programmable phase-slope limiting
Programmable tracking range (i.e. hold-in range)
Truly hitless reference switching with <200ps output clock phase transient
Output phase adjustment in 10ps steps
High-resolution frequency and phase measurement
Fast detection of input clock failure and transition to holdover mode
Holdover frequency averaging with programmable averaging time and delay time
APLL with very high-resolution fractional scaling (i.e. non-integer) per channel
Any-to-any frequency conversion with 0ppm error
Two high-speed dividers (integers 4 to 15, half divides 4.5 to 7.5)
Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter
components
Bypass mode supports system testing
Three low-jitter output clocks per channel
Each output can be one differential output or two CMOS outputs
Output clocks can be any frequency from 1Hz to 1035MHz (250MHz max for CMOS and HSTL outputs)
Output jitter as low as 0.25ps RMS (12kHz to 20MHz)
2.2
DPLL Features
2.3
APLL Features
2.4
Output Clock Features
2
Microsemi Corporation
ZL30623
Product Brief
In CMOS mode, an additional divider allows the OCxN pin to be an integer divisor of the OCxP pin
(Example 1: OC3P 125MHz, OC3N 25MHz. Example 2: OC2P 25MHz, OC2N 1Hz)
Outputs easily interface with CML, LVDS, LVPECL, HSTL, SSTL, HCSL and CMOS components
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN
Sophisticated output-to-output phase alignment
Per-output phase adjustment with high resolution and unlimited range
Per-output enable/disable
Per-output glitchless start/stop (stop high or low)
SPI or I C serial microprocessor interface per channel
Automatic self-configuration at power-up from internal EEPROM memory; pin control to specify one of
four stored configurations
Each channel can be configured for numerically controlled oscillator (NCO) mode, which allows system
software to steer frequency with resolution better than 0.01ppb
Four general-purpose I/O pins per channel each with many possible status and control options
Output frame sync signals: 2kHz or 8kHz (SONET/SDH), 1Hz (IEEE 1588) or other frequency
Internal compensation for local os
cill
ator frequency error
2
2.5
General Features
2.6
Evaluation Software
Simple, intuitive Windows-based graphical user interface
Supports all device features and register fields
Makes lab evaluation of the ZL30623 quick and easy
Generates configuration scripts to be stored in internal EEPROM
Generates full or partial configuration scripts to be run on a system processor
Works with or without a ZL30623 evaluation board
3
Microsemi Corporation
ZL30623
3. Pin Diagram
The device is packaged in a 5x10mm 64-pin LGA.
TEST/GPIO2_B
IC3P/GPIO3_A
AC0/GPIO0_B
AC1/GPIO1_B
SDA_MOSI_A
Product Brief
SCL/SCLK_A
IF1/MISO_A
DVDD33_A
DVDD18_A
AVDD33_B
IF0/CSN_A
VDDO1_B
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
VDDXO33_A
XA_A
XB_A
AVDD18_A
AVDD18_A
OC3N_A
OC3P_A
VDDO3_A
AVDD18_A
AVDD18_A
VDDO2_B
OC1N_B
OC2N_B
OC1P_B
OC2P_B
RSTN_A
IC1N_A
IC2N_A
IC1P_A
IC2P_A
55
56
57
58
59
60
61
VSS_A (E-pad)
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VSS_B (E-pad)
AVDD18_B
AVDD18_B
VDDO3_B
OC3P_B
OC3N_B
AVDD18_B
AVDD18_B
XB_B
XA_B
VDDXO33_B
25
24
23
TEST/GPIO2_A
AC1/GPIO1_A
IF1/MISO_B
SDA/MOSI_B
IC3P/GPIO3_B
SCL/SCLK_B
VDDO2_A
OC2P_A
OC2N_A
AVDD33_A
OC1N_A
OC1P_A
DVDD18_B
RSTN_B
IF0/CSN_B
DVDD33_B
IC2N_B
IC2P_B
IC1N_B
VDDO1_A
Figure 3 - Pin Diagram
AC0/GPIO0_A
4
Microsemi Corporation
IC1P_B
ZL30623
4. Mechanical Drawing
Product Brief
TOTAL THICKNESS
SUBSTRATE THICKNESS
MOLD THICKNESS
BODY SIZE
LEAD WIDTH
LEAD LENGTH
LEAD PITCH
LEAD COUNT
EDGE LEAD CENTER TO
CENTER
BODY CENTER TO LEAD
PACKAGE EDGE TOLERANCE
MOLD FLATNESS
COPLANARITY
Dimensions in mm.
SYMBOL
A
A1
A2
D
E
W
L
e
n
D1
E1
SD
SE
aaa
bbb
ddd
COMMON DIMENSIONS
MIN
TYP
MAX
---
---
1
0.19
REF
0.7
REF
10
BSC
5
BSC
0.2
0.25
0.3
0.35
0.4
0.45
0.4
BSC
64
8.4
BSC
3.6
BSC
0.2
BSC
0.2
BSC
0.1
0.2
0.08
5
Microsemi Corporation
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