eGaN® FET DATASHEET
EPC2022
EPC2022 – Enhancement Mode Power Transistor
V
DSS
, 100 V
R
DS(on)
, 3.2 mΩ
I
D
, 90 A
Gallium Nitride is grown on Silicon Wafers and processed using standard CMOS equipment
leveraging the infrastructure that has been developed over the last 60 years. GaN’s exceptionally
high electron mobility and low temperature coefficient allows very low R
DS(on)
, while its lateral device
structure and majority carrier diode provide exceptionally low Q
G
and zero Q
RR
. The end result is a
device that can handle tasks where very high switching frequency, and low on-time are beneficial
as well as those where on-state losses dominate.
Maximum Ratings
V
DS
I
D
V
GS
T
J
T
STG
Drain-to-Source Voltage (Continuous)
Drain-to-Source Voltage (up to 10,000 5 ms pulses at 150˚C)
Continuous (T
A
= 25˚C, R
θJA
= 2.5˚C/W)
Pulsed (25˚C, T
PULSE
= 300 µs)
Gate-to-Source Voltage
Gate-to-Source Voltage
Operating Temperature
Storage Temperature
100
120
90
390
6
-4
-40 to 150
-40 to 150
V
EFFICIENT POWER CONVERSION
HAL
EPC2022 eGaN® FETs are supplied only in
passivated die form with solder bumps.
Die Size: 6.05 mm x 2.3 mm
•
•
•
•
•
•
High Speed DC-DC Conversion
Motor Drive
Industrial Automation
Synchronous Rectification
Inrush Protection
Class-D Audio
A
V
˚C
www.epc-co.com/epc/Products/eGaNFETs/EPC2022.aspx
Static Characteristics
(T
J
= 25˚C unless otherwise stated)
PARAMETER
BV
DSS
I
DSS
I
GSS
V
GS(TH)
R
DS(on)
V
SD
Drain-to-Source Voltage
Drain Source Leakage
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Gate Threshold Voltage
Drain-to-Source On Resistance
Source-to-Drain Forward Voltage
TEST CONDITIONS
V
GS
= 0 V, I
D
= 0.9 mA
V
DS
= 80 V, V
GS
= 0 V
V
GS
= 5 V
V
GS
= -4 V
V
DS
= V
GS
, I
D
= 13 mA
V
GS
= 5 V, I
D
= 25 A
I
S
= 0.5 A, V
GS
= 0 V
0.8
MIN
100
0.1
1
0.1
1.4
2.4
1.8
0.7
9
0.7
2.5
3.2
TYP
MAX
UNIT
V
mA
mA
mA
V
mΩ
V
All measurements were done with substrate shorted to source.
Thermal Characteristics
TYP
R
θ
JC
R
θ
JB
R
θ
JA
Thermal Resistance, Junction to Case
Thermal Resistance, Junction to Board
Thermal Resistance, Junction to Ambient (Note 1)
0.4
1.1
42
UNIT
˚C/W
˚C/W
˚C/W
Note 1: R
θ
JA
is determined with the device mounted on one square inch of copper pad, single layer 2 oz copper on FR4 board.
See http://epc-co.com/epc/documents/product-training/Appnote_Thermal_Performance_of_eGaN_FETs.pdf for details.
EPC – EFFICIENT POWER CONVERSION CORPORATION |
WWW.EPC-CO.COM
| COPYRIGHT 2016 |
| 1
eGaN® FET DATASHEET
Dynamic Characteristics
(T
J
= 25˚C unless otherwise stated)
PARAMETER
C
ISS
C
RSS
C
OSS
C
OSS(ER)
C
OSS(TR)
R
G
Q
G
Q
GS
Q
GD
Q
G(TH)
Q
OSS
Q
RR
Input Capacitance
Reverse Transfer Capacitance
Output Capacitance
E ective Output Capacitance,
Enegy Related (Note 2)
E ective Output Capacitance,
Time Related (Note 3)
Gate Resistance
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain Charge
Gate Charge at Threshold
Output Charge
Source-to-Drain Recovery Charge
V
DS
= 50 V, V
GS
= 0 V
V
DS
= 50 V, I
D
= 25 A
V
DS
= 50 V, V
GS
= 5 V, I
D
= 25 A
V
DS
= 50 V, V
GS
= 0 V
TEST CONDITIONS
MIN
TYP
1400
7
840
1090
EPC2022
MAX
1680
1260
UNIT
pF
V
DS
= 0 to 50 V, V
GS
= 0 V
1410
0.3
13
3.4
2.4
2.1
71
0
16
nC
107
Note 2: C
OSS(ER)
is a xed capacitance that gives the same stored energy as C
oss
while V
DS
is rising from 0 to 50% BV
DSS
.
Note 3: C
OSS(TR)
is a xed capacitance that gives the same charging time as C
oss
while V
DS
is rising from 0 to 50% BV
DSS
.
Figure 1: Typical Output Characteristics at 25°C
Figure 2: Transfer Characteristics
300
300
25˚C
125˚C
V
DS
= 3 V
I
D
– Drain Current (A)
I
D
– Drain Current (A)
200
V
GS
= 5 V
V
GS
= 4 V
V
GS
= 3 V
V
GS
= 2 V
200
100
100
0
0
0.5
V
DS
– Drain-to-Source Voltage (V)
1.0
1.5
2.0
2.5
3.0
0
0.5
1.0
1.5
V
GS
– Gate-to-Source Voltage (V)
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Figure 3: R
DS(on)
vs. V
GS
for Various Drain Currents
R
DS(on)
– Drain-to-Source Resistance (m )
R
DS(on)
– Drain-to-Source Resistance (m )
Figure 4: R
DS(on)
vs. V
GS
for Various Temperatures
8
6
I
D
= 25 A
I
D
= 50 A
I
D
= 100 A
I
D
= 150 A
8
25˚C
125˚C
I
D
= 25 V
V
DS
= 3 A
6
4
4
2
2
0
2.5
3.0
3.5
4.0
4.5
5.0
0
V
GS
– Gate-to-Source Voltage (V)
2.0
2.5
V
GS
– Gate-to-Source Voltage (V)
3.0
3.5
4.0
4.5
5.0
EPC – EFFICIENT POWER CONVERSION CORPORATION |
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| COPYRIGHT 2016 |
| 2
eGaN® FET DATASHEET
Figure 5a: Capacitance (Linear Scale)
2500
C
OSS
= C
GD
+ C
SD
C
ISS
= C
GD
+ C
GS
C
RSS
= C
GD
1000
EPC2022
Figure 5b: Capacitance (Log Scale)
2000
Capacitance (pF)
Capacitance (pF)
1500
100
C
OSS
= C
GD
+ C
SD
C
ISS
= C
GD
+ C
GS
C
RSS
= C
GD
1000
10
500
0
0
20
40
60
80
100
1
0
20
40
60
80
100
V
DS
– Drain-to-Source Voltage (V)
V
DS
– Drain-to-Source Voltage (V)
Figure 6: Gate Charge
5
I
D
= 25 A
V
DS
= 50 V
Figure 7: Reverse Drain-Source Characteristics
V
GS
–
Gate-to-Source Voltage (V)
I
SD
– Source-to-Drain Current (A)
4
300
25˚C
125˚C
V
GS
= 0 V
3
200
2
100
1
0
0
5
10
15
0
Q
G
– Gate Charge (nC)
0
0.5
1.0
V
SD
– Source-to-Drain Voltage (V)
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Figure 8: Normalized On-State Resistance vs. Temperature
2.0
1.40
I
D
= 25 A
V
GS
= 5 V
1.30
Figure 9: Normalized Threshold Voltage vs. Temperature
I
D
= 13 mA
Normalized On-State Resistance R
DS(on)
1.8
1.6
1.4
1.2
1.0
0.8
Normalized Threshold Voltage
25
50
75
100
125
150
1.20
1.10
1.00
0.90
0.80
0.70
0
0.60
T
J
– Junction Temperature (°C)
0
25
T
J
– Junction Temperature (°C)
50
75
100
125
150
All measurements were done with substrate shortened to source.
EPC – EFFICIENT POWER CONVERSION CORPORATION |
WWW.EPC-CO.COM
| COPYRIGHT 2016 |
| 3
eGaN® FET DATASHEET
EPC2022
Figure 10: Gate Leakage Current
60
50
25˚C
125˚C
Figure 11: Safe Operating Area
1000
I
G
– Gate Current (mA)
40
30
20
10
0
I
D
– Drain Current (A)
100
Limited by R
DS(on)
10
Pulse Width
100 ms
10 ms
1 ms
100 µs
1
0
1
V
GS
– Gate-to-Source Voltage (V)
2
3
4
5
6
0.1
0.1
1
10
100
V
DS
- Drain-Source Voltage (V)
T
J
= Max Rated, T
C
= +25°C, Single Pulse
Figure 12: Transient Thermal Response Curves
Junction-to-Board
Z
θJB
, Normalized Thermal Impedance
1
Duty Cycle:
0.5
0.1
0.05
0.02
0.01
0.01
0.001
Single Pulse
0.0001
10
-5
0.1
P
DM
t
1
t
2
Notes:
Duty Factor: D = t
1
/t
2
Peak T
J
= P
DM
x Z
θJB
x R
θJB
+ T
B
10
-4
10
-3
10
-2
10
-1
1
10
+1
t
p
, Rectangular Pulse Duration, seconds
Junction-to-Case
Z
θJC
, Normalized Thermal Impedance
1
Duty Cycle:
0.5
0.2
0.1
0.1
0.05
0.02
0.01
0.01
0.001
P
DM
t
1
t
2
Single Pulse
0.0001
10
-6
Notes:
Duty Factor: D = t
1
/t
2
Peak T
J
= P
DM
x Z
θJC
x R
θJC
+ T
C
10
-5
10
-4
10
-3
10
-2
10
-1
1
t
p
, Rectangular Pulse Duration, seconds
EPC – EFFICIENT POWER CONVERSION CORPORATION |
WWW.EPC-CO.COM
| COPYRIGHT 2016 |
| 4
eGaN® FET DATASHEET
TAPE AND REEL CONFIGURATION
4mm pitch, 12mm wide tape on 7” reel
EPC2022
b
d
e
f
g
Loaded Tape Feed Direction
7” reel
Die
orientation
dot
Gate
solder bar is
under this
corner
Dimension (mm) target min
EPC2022 (note 1)
12.00
1.75
5.50
4.00
4.00
2.00
1.50
11.70
1.65
5.45
3.90
3.90
1.95
1.50
a
b
c (see note)
d
e
f (see note)
g
12.30
1.85
5.55
4.10
4.10
2.05
1.60
max
Die is placed into pocket
solder bar side down
(face side down)
Note 1: MSL 1 (moisture sensitivity level 1) classi ed according to IPC/JEDEC industry standard.
Note 2: Pocket position is relative to the sprocket hole measured as true position of the pocket,
not the pocket hole.
DIE MARKINGS
2022
Die orientation dot
Gate Pad bump is
under this corner
YYYY
ZZZZ
Part
Number
EPC2022
Laser Marking
Part #
Marking Line 1
2022
Lot_Date Code
Marking Line 2
YYYY
Lot_Date Code
Marking Line 3
ZZZZ
DIE OUTLINE
Solder Bump View
A
f
X30
DIM
A
B
c
d
e
f
g
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
c
X30
d
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
B
Pad 1 is Gate
e
X4
g
X28
Pads 2,5,6,9,10,13,14,17,18,21,22,
25,26,29 are Source
(685)
(785)
Side View
Pads 3,4,7,8,11,12,15,16,19,20,23,
24,27,28 are Drain
Pad 30 is Substrate
SEATING PLANE
EPC – EFFICIENT POWER CONVERSION CORPORATION |
WWW.EPC-CO.COM
| COPYRIGHT 2016 |
100 ± 20
YYYY
2022
MIN
6020
2270
2047
717
210
195
400
a
c
ZZZZ
Micrometers
Nominal
6050
2300
2050
720
225
200
400
MAX
6080
2330
2053
723
240
205
400
| 5
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