XCR5128C-15TQ128C datasheet, PDF

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XCR5128C-15TQ128C: Description128 Macrocell CPLD with Enhanced Clocking; File Size270KB，19 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XCR5128C-15TQ128C Overview

128 Macrocell CPLD with Enhanced Clocking

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ds042.fm Page 1 Monday, October 9, 2000 8:26 PM

This product has been discontinued. Please see

www.xilinx.com/partinfo/notify/pdn0007.htm

for details.

APPLICATION NOTE

XCR5128C: 128 Macrocell

CPLD with Enhanced Clocking

14*

DS042 (v1.3) October 9, 2000

Product Specification

Features

•

Industry's first TotalCMOS™ PLD - both CMOS design

and process technologies

Fast Zero Power (FZP™) design technique provides

ultra-low power and very high speed

5V, In-System Programmable (ISP) using a JTAG

interface

- On-chip supervoltage generation

- ISP commands include: Enable, Erase, Program,

Verify

- Supported by multiple ISP programming platforms

- Four pin JTAG interface (TCK, TMS, TDI, TDO)

- JTAG commands include: Bypass, Idcode

High speed pin-to-pin delays of 7.5 ns

Ultra-low static power of less than 100

100% routable with 100% utilization while all pins and

all macrocells are fixed

Deterministic timing model that is extremely simple to

use

Up to 20 clocks available

Support for complex asynchronous clocking

Innovative XPLA™ architecture combines high speed

with extreme flexibility

1000 erase/program cycles guaranteed

20 years data retention guaranteed

Logic expandable to 37 product terms

PCI compliant

Advanced 0.5

CMOS process

Security bit prevents unauthorized access

Design entry and verification using industry standard

and Xilinx CAE tools

Reprogrammable using industry standard device

programmers

Innovative Control Term structure provides either sum

terms or product terms in each logic block for:

- Programmable 3-state buffer

- Asynchronous macrocell register preset/reset

- Up to two asynchronous clocks

Programmable global 3-state pin facilitates `bed of

nails' testing without using logic resources

Available in TQFP and LQFP packages

Available in both Commercial and Industrial grades

Description

The XCR5128C CPLD (Complex Programmable Logic

Device) is a member of the CoolRunner

family of CPLDs

from Xilinx. These devices combine high speed and zero

power in a 128 macrocell CPLD. With the FZP design tech-

nique, the XCR5128C offers true pin-to-pin speeds of 7.5

ns, while simultaneously delivering power that is less than

100

A at standby without the need for “turbo bits” or other

power down schemes. By replacing conventional sense

amplifier methods for implementing product terms (a tech-

nique that has been used in PLDs since the bipolar era)

with a cascaded chain of pure CMOS gates, the dynamic

power is also substantially lower than any competing

CPLD. These devices are the first TotalCMOS PLDs, as

they use both a CMOS process technology

and

the pat-

ented full CMOS FZP design technique.

The Xilinx FZP CPLDs utilize the patented XPLA

(eXtended Programmable Logic Array) architecture. The

XPLA architecture combines the best features of both PLA

and PAL type structures to deliver high speed and flexible

logic allocation that results in superior ability to make

design changes with fixed pinouts. The XPLA structure in

each logic block provides a fast 7.5 ns PAL path with five

dedicated product terms per output. This PAL path is joined

by an additional PLA structure that deploys a pool of 32

product terms to a fully programmable OR array that can

allocate the PLA product terms to any output in the logic

block. This combination allows logic to be allocated effi-

ciently throughout the logic block and supports as many as

37 product terms on an output. The speed with which logic

is allocated from the PLA array to an output is only 2ns,

regardless of the number of PLA product terms used, which

results in worst case t

's of only 9.5 ns from any pin to any

other pin. In addition, logic that is common to multiple out-

puts can be placed on a single PLA product term and

shared across multiple outputs via the OR array, effectively

increasing design density.

The XCR5128C CPLDs are supported by industry standard

CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,

Synopsys, Synario, Viewlogic, and Synplicity), using text

(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-

ification uses industry standard simulators for functional

and timing simulation. Development is supported on per-

sonal computer, Sparc, and HP platforms. Device fitting

uses Xilinx developed tools including WebFITTER.

The XCR5128C CPLD is electrically reprogrammable

using industry standard device programmers from vendors

•

DS042 (v1.3) October 9, 2000

www.xilinx.com

1-800-255-7778

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