Datasheet
RX113 Group
Renesas MCUs
R01DS0216EJ0110
Rev.1.10
Mar 31, 2016
32 MHz, 32-bit RX MCUs, 50 DMIPS, up to 512 Kbytes of flash memory,
USB 2.0 full-speed host/function/OTG, up to 12 comms channels, serial sound interface,
LCD controller/driver, capacitive touch sensing unit, 12-bit A/D, 12-bit D/A, RTC
Features
■
32-bit RX CPU core
32 MHz maximum operating frequency
Capable of 50 DMIPS when operating at 32 MHz
Accumulator handles 64-bit results (for a single instruction) from 32-
bit × 32-bit operations
Multiplication and division unit handles 32-bit × 32-bit operations
(multiplication instructions take one CPU clock cycle)
Fast interrupt
CISC Harvard architecture with five-stage pipeline
Variable-length instruction format, ultra-compact code
On-chip debugging circuit
PLQP0100KB-A 14 × 14 mm, 0.5 mm pitch
PLQP0064KB-A 10 × 10 mm, 0.5 mm pitch
■
Low power consumption functions
PTLG0100JA-A
7 × 7 mm, 0.65 mm pitch
Operation from a single 1.8 to 3.6 V supply
Three low power consumption modes
Low power timer (LPT) that operates during the software standby
state
Supply current
High-speed operating mode: 0.11 mA/MHz
Software standby mode: 0.44
μA
Recovery time from software standby mode: 4.8
μs
Operation at 32 MHz, read cycle of 31.25 ns
No wait states for reading at full CPU speed
128 to 512 Kbyte capacities
Programmable at 1.8 V
For instructions and operands
■
Up to 12 channels for communication
■
On-chip flash memory for code, no wait states
USB: USB 2.0 host/function/On-The-Go (OTG) (one channel), full-
speed = 12 Mbps, low-speed = 1.5 Mbps, isochronous transfer, and
BC (Battery Charger) supported
SCI: Asynchronous mode, clock synchronous mode, smart card
interface (up to eight channels)
IrDA interface (one channel, in cooperation with SCI5)
I
2
C bus interface: Transfer at up to 400 kbps, capable of SMBus
operation (one channel)
RSPI: Up to 16 Mbps (one channel)
Serial sound interface (SSI) (one channel)
16-bit MTU: Input capture/output compare, complementary PWM
output, phase counting mode
(six channels)
8-bit TMR (four channels)
16-bit CMT (four channels)
Segment signal output × common signal output:
40 × 4, 36 × 8
On-chip voltage boost circuit, contrast adjustment, and 5-V panel
supported
Blinking function
Up to 17 channels
1.0
μs
minimum conversion speed
Double trigger (data duplication) function for motor control
Two channels
Two channels
■
On-chip data flash memory
■
Up to 14 extended-function timers
8 Kbytes
1,000,000 Erase/Write cycles (typ.)
BGO (Background Operation)
32 and 64 Kbyte capacities
■
On-chip SRAM, no wait states
■
Data transfer controller (DTC)
■
Event link controller (ELC)
Four transfer modes
Transfer can be set for each interrupt source.
Module operation can be initiated by event signals without going
through interrupts.
Link operation between modules is possible while the CPU is
sleeping.
Six types including Power-On Reset (POR)
Low voltage detection (LVD) with voltage settings
■
LCD controller/driver
■
12-bit A/D converter
■
Reset and power supply voltage management
■
Clock functions
External clock input frequency: Up to 20 MHz
Main clock oscillator frequency: 1 to 20 MHz
Sub-clock oscillator frequency: 32.768 kHz
PLL circuit input: 4 to 8 MHz
Low-speed on-chip oscillator: 4 MHz
High-speed on-chip oscillator: 32 MHz ±1% (20 to 85°C)
USB-dedicated PLL circuit: 6 and 8 MHz
IWDT-dedicated on-chip oscillator: 15 kHz
Generate a dedicated 32.768-kHz clock for the RTC
On-chip clock frequency accuracy measurement circuit (CAC)
■
12-bit D/A converter
■
Comparator B
■
Capacitive touch sensing unit (CTSU)
Detection pins: 12 channels (for 100 pins only)
High-sensitive electrostatic capacitance detection using
self-capacitance and mutual capacitance methods
On-chip noise canceller that enables high tolerance to disturbance
noise
Also supports a mutual capacitance method that allows touch
channels to be increased with low pin counts
■
Realtime clock (RTC)
30-second, leap year, and error adjustment functions
Calendar count mode or binary count mode selectable
Capable of initiating exit from software standby mode
15-kHz on-chip oscillator produces a dedicated clock signal to drive
IWDT operation.
Clock frequency accuracy measurement circuit, IWDT, functions to
assist in RAM testing, etc.
■
Temperature sensor
■
General I/O ports
5-V tolerant, open drain, input pull-up
Multiple I/O pins can be selected for peripheral functions.
32-byte ID code for the MCU
40
to
85C
40
to
105°C
■
Multi-function pin controller (MPC)
■
Unique ID
■
Independent watchdog timer (IWDT)
■
On-chip functions for IEC 60730 compliance
■
Operating temperature range
R01DS0216EJ0110 Rev.1.10
Mar 31, 2016
Page 1 of 131
RX113 Group
1. Overview
1.
1.1
Overview
Outline of Specifications
Table 1.1
lists the specifications, and
Table 1.2
gives a comparison of the functions of the products in different
packages.
Table 1.1
is for products with the greatest number of functions, so the number of peripheral modules and channels will
differ in accordance with the package type. For details, see
Table 1.2, Comparison of Functions for Different
Packages.
Table 1.1
Classification
CPU
Outline of Specifications (1/3)
Module/Function
CPU
Description
Maximum operating frequency: 32 MHz
32-bit RX CPU
Minimum instruction execution time: One instruction per clock cycle
Address space: 4-Gbyte linear
Register set
General purpose: Sixteen 32-bit registers
Control: Eight 32-bit registers
Accumulator: One 64-bit register
Basic instructions: 73
DSP instructions: 9
Addressing modes: 10
Data arrangement
Instructions: Little endian
Data: Selectable as little endian or big endian
On-chip 32-bit multiplier: 32-bit × 32-bit
→
64-bit
On-chip divider: 32-bit ÷ 32-bit
→
32 bits
Barrel shifter: 32 bits
Memory
ROM
Capacity: 128 K /256 K /384 K /512 Kbytes
32 MHz, no-wait memory access
Programming/erasing method:
Serial programming (asynchronous serial communication/USB communication), self-programming
Capacity: 32 K /64 Kbytes
32 MHz, no-wait memory access
Capacity: 8 Kbytes
Number of erase/write cycles: 1,000,000 (typ)
Single-chip mode
Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,
PLL frequency synthesizer, USB-dedicated PLL frequency synthesizer, and IWDT-dedicated on-chip
oscillator
Oscillation stop detection: Available
Clock frequency accuracy measurement circuit (CAC)
Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock
(FCLK)
The CPU and system sections such as other bus masters run in synchronization with the system
clock (ICLK): 32 MHz (at max.)
Peripheral modules run in synchronization with the PCLK: 32 MHz (at max.)
The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)
The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1, 2, 4, 8, 16, 32,
64).
RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and
software reset
RAM
E2 DataFlash
MCU operating mode
Clock
Clock generation circuit
Resets
Voltage detection
Voltage detection circuit
(LVDAa)
When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt
is generated.
Voltage detection circuit 1 is capable of selecting the detection voltage from 10 levels
Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels
Module stop function
Three low power consumption modes
Sleep mode, deep sleep mode, and software standby mode
Operating power control modes
High-speed operating mode, middle-speed operating mode, and low-speed operating mode
Interrupt vectors: 120
External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)
Non-maskable interrupts: 4 (NMI pin, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt,
and IWDT interrupt)
16 levels specifiable for the order of priority
Low power
consumption
Low power consumption
functions
Function for lower operating
power consumption
Interrupt
Interrupt controller (ICUb)
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Mar 31, 2016
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RX113 Group
Table 1.1
Classification
DMA
1. Overview
Outline of Specifications (2/3)
Module/Function
Data transfer controller
(DTCa)
General I/O ports
Description
Transfer modes: Normal transfer, repeat transfer, and block transfer
Activation sources: Interrupts
Chain transfer function
100-pin /64-pin
I/O: 82/46
Input: 2/2
Pull-up resistors: 69/38
Open-drain outputs: 61/34
5-V tolerance: 4/4
Event signals of 44 types can be directly connected to the module
Operations of timer modules are selectable at event input
Capable of event link operation for port B
Capable of selecting the input/output function from multiple pins
(16 bits × 6 channels) × 1 unit
Time bases for the six 16-bit timer channels can be provided via up to 16 pulse-input/output lines and
three pulse-input lines
Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,
PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than
channel 5, for which only four signals are available.
Input capture function
21 output compare/input capture registers
Pulse output mode
Complementary PWM output mode
Reset synchronous PWM mode
Phase-counting mode
Capable of generating conversion start triggers for the A/D converter
Controls the high-impedance state of the MTU’s waveform output pins
(16 bits × 2 channels) × 2 units
Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)
14 bits × 1 channel
Count clock: Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 1, 16, 32, 64, 128, or 256
Clock source: Sub-clock
Calendar count mode or binary count mode selectable
Interrupts: Alarm interrupt, periodic interrupt, and carry interrupt
16 bits × 1 channel
Clock source: Sub-clock, Dedicated low-speed on-chip oscillator for the IWDT
Frequency divided by 2, 4, 8, 16, or 32
(8 bits × 2 channels) × 2 units
Seven internal clocks (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, and PCLK/8192)
and an external clock can be selected
Pulse output and PWM output with any duty cycle are available
Two channels can be cascaded and used as a 16-bit timer
8 channels (channel 0, 1, 2, 5, 6, 8, and 9: SCIe, channel 12: SCIf)
Serial communications modes: Asynchronous, clock synchronous, and smart card interface
On-chip baud rate generator allows selection of the desired bit rate
Choice of LSB-first or MSB-first transfer
Average transfer rate clock can be input from MTU2 timers
Simple I
2
C
Simple SPI
Master/slave mode supported (SCIf only)
Start frame and information frame are included (SCIf only)
Start-bit detection in asynchronous mode: Low level or falling edge is selectable
I/O ports
Event link controller (ELC)
Multi-function pin controller (MPC)
Timers
Multi-function timer pulse
unit 2 (MTU2a)
Port output enable 2
(POE2a)
Compare match timer
(CMT)
Independent watchdog
timer (IWDTa)
Realtime clock (RTCA)
Low power timer (LPT)
8-bit timer (TMR)
Communication
functions
Serial communications
interfaces (SCIe, SCIf)
IrDA interface (IRDA)
I
2
C bus interface (RIIC)
1 channel (SCI5 used)
Supports encoding/decoding of waveforms conforming to IrDA standard 1.0
1 channel
Communications formats:
I
2
C bus format/SMBus format
Master mode or slave mode selectable
Supports fast mode
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Mar 31, 2016
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RX113 Group
Table 1.1
Classification
Communication
functions
1. Overview
Outline of Specifications (3/3)
Module/Function
Serial peripheral interface
(RSPI)
Description
1 channel
Transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select), and RSPI
clock (RSPCK) signals enables serial transfer through SPI operation (four lines) or clock-
synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
Data formats
Choice of LSB-first or MSB-first transfer
The number of bits in each transfer can be changed to 8, 9, 10, 11, 12, 13, 14, 15, 16, 20, 24, or
32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each frame
having up to 32 bits)
Double buffers for both transmission and reception
USB Device Controller (UDC) and transceiver for USB 2.0 are incorporated.
Host/function module: 1 port
Compliant with USB version 2.0
Transfer speed: Full-speed (12 Mbps), low-speed (1.5 Mbps)
OTG (ON-The-Go) is supported.
Isochronous transfer is supported.
BC (Battery Charger) is supported.
1 channel
Capable of duplex communications
Various serial audio formats supported
Master/slave function supported
Programmable word clock or bit clock generation function
8/16/18/20/22/24/32-bit data formats supported
On-chip 8-stage FIFO for transmission/reception
Supports WS continue mode in which the SSIWS signal is not stopped.
USB 2.0 host/function
module (USBc)
Serial Sound Interface (SSI)
LCD controller/driver (LCDC)
Internal voltage boosting method, capacitor split method, and external resistance division method are
switchable.
Segment signal output × common signal output: 40 × 4, 36 × 8
1 unit (1 unit × 17 channels)
12-bit resolution
Minimum conversion time: 1.0 µs per channel when the ADCLK is operating at 32 MHz
Operating modes
Scan mode (single scan mode, continuous scan mode, and group scan mode)
Double trigger mode (duplication of A/D conversion data)
A/D conversion start conditions
A software trigger, a trigger from a timer (MTU), an external trigger signal, or ELC
1 channel
The voltage of the temperature is converted into a digital value by the 12-bit A/D converter.
2 channels
12-bit resolution
Output voltage: 0.35 to AVCC - 0.47 V
CRC code generation for arbitrary amounts of data in 8-bit units
Select any of three generating polynomials:
X
8
+ X
2
+ X + 1, X
16
+ X
15
+ X
2
+ 1, or X
16
+ X
12
+ X
5
+ 1
Generation of CRC codes for use with LSB-first or MSB-first communications is selectable.
2 channels
Function to compare the reference voltage and the analog input voltage
Window comparator operation or standard comparator operation is selectable
Detection pin: 12 channels (for 100 pins only)
Comparison, addition, and subtraction of 16-bit data
32-byte ID code for the MCU
VCC = 1.8 to 2.4 V: 8 MHz, VCC = 2.4 to 2.7 V: 16 MHz, VCC = 2.7 to 3.6 V: 32 MHz
3.6 mA at 32 MHz (typ.)
D version:
40
to +85°C, G version:
40
to +105°C
100-pin LFQFP (PLQP0100KB-A) 14 × 14 mm, 0.50 mm pitch
100-pin TFLGA (PTLG0100JA-A) 7 × 7 mm, 0.65 mm pitch
64-pin LFQFP (PLQP0064KB-A) 10 × 10 mm, 0.50 mm pitch
E1 emulator (FINE interface)
12-bit A/D converter (S12ADb)
Temperature sensor (TEMPSA)
12-bit D/A converter (R12DAA)
CRC calculator (CRC)
Comparator B (CMPBa)
Capacitive touch sensing unit (CTSU)
Data operation circuit (DOC)
Unique ID
Power supply voltages/Operating frequencies
Supply current
Operating temperature range
Packages
On-chip debugging system
R01DS0216EJ0110 Rev.1.10
Mar 31, 2016
Page 4 of 131
RX113 Group
Table 1.2
Comparison of Functions for Different Packages
RX113 Group
Module/Functions
Interrupts
DMA
Timers
External interrupts
Data transfer controller
Multi-function timer pulse unit 2
Port output enable 2
Compare match timer
Realtime clock
Low power timer
8-bit timer
Independent watchdog timer
Communication
functions
Serial communications interfaces (SCIe)
[simple I
2
C, simple SPI]
IrDA interface
Serial communications interface (SCIf)
[simple I
2
C, simple SPI]
I
2
C bus interface
Serial peripheral interface
USB 2.0 host/function module (USBc)
Serial sound interface
12-bit A/D converter
(including high-precision channels)
Temperature sensor
Comparator B
12-bit D/A converter
CRC calculator
Event link controller
Capacitive touch sensing unit
LCD
Packages
12 channels
40 SEG × 4 COM
36 SEG × 8 COM
100-pin LFQFP
100-pin TFLGA
17 channels
(9 channels)
Supported
2 channels
2 channels
Supported
Supported
7 channels
(SCI0, 1, 2, 5, 6, 8, 9)
1 channel (SCI5)
1 channel (SCI12)
1 channel
1 channel
1 channel
1 channel
11 channels
(3 channels)
100 Pins
NMI, IRQ0 to IRQ7
Supported
6 channels (MTU0 to MTU5)
Supported
2 channels × 2 units
Supported
1 channel
2 channels × 2 units
Supported
64 Pins
1. Overview
5 channels
(SCI1, 5, 6, 8, 9)
Not supported
20 SEG × 4 COM
16 SEG × 8 COM
64-pin LFQFP
R01DS0216EJ0110 Rev.1.10
Mar 31, 2016
Page 5 of 131
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