1:2 Clock Fanout Buffer and
Frequency Divider
8T73S1802
Datasheet
Description
The 8T73S1802 is a fully integrated clock fanout buffer and
frequency divider. The input signal is frequency-divided and then
fanned out to one differential LVPECL and one LVCMOS output.
Each of the outputs can select its individual divider value from the
range of ÷1, ÷2, ÷4 and ÷8. Three control inputs EN, SEL0 and
SEL1 (3-level logic) are available to select the frequency dividers
and the output enable/disable state. The single-ended LVCMOS
output is phase-delayed by 650ps to minimize coupling of
LVCMOS switching into the differential output during its signal
transition.
The 8T73S1802 is optimized to deliver very low phase noise
clocks. The V
BB
output generates a common-mode voltage
reference for the differential clock input so that connecting the V
BB
pin to an unused input (nCLK) enables to use of single-ended input
signals. The extended temperature range supports wireless
infrastructure, telecommunication and networking end equipment
requirements. The 8T73S1802 can be used with a 3.3V or a 2.5V
power supply. The device is a member of the high-performance
clock family from IDT.
Features
• High-performance fanout buffer clock and fanout buffer
• Input clock signal is distributed to one LVPECL and one
LVCMOS output
• Configurable output dividers for both LVPECL and LVCMOS
outputs
• Supports clock frequencies up to 1000MHz (LVPECL) and up to
200MHz (LVCMOS)
• Flexible differential input supports LVPECL, LVDS and CML
• V
BB
generator output supports single-ended input signal
applications
• Optimized for low phase noise
• 650ps delay between LVCMOS and LVPECL minimizes coupling
between outputs
• Supply voltage: 3.3V or 2.5V
• -40°C to 85°C ambient operating temperature
• 16 VFQFPN package (3 x 3 mm)
Block Diagram
Pin Assignment
V
CCO_QA
V
CCO_QA
9
8
7
nQA
11
CLK
nCLK
÷1
÷2
÷4
÷8
QA
nQA
12
SEL0
GND
13
14
QA
10
V
CCO_QB
QB
GND
GND
V
BB
Bias Generator
V
CC
-1.3V
8T73S1802
QB
SEL1
EN
15
16
1
8XXXXXX
2
3
4
6
5
V
CC
nCLK
16-pin, 3mm x 3mm VFQFPN Package
©2018 Integrated Device Technology, Inc.
1
CLK
V
BB
SEL0
SEL1
EN
Pullup
Pullup
Pullup
Control
January 21, 2018
8T73S1802 Datasheet
Pin Description and Pin Characteristic Tables
Table 1. Pin Assignment
Pin Number
1
2
3
4
5
6
Name
V
CC
CLK
nCLK
V
BB
GND
GND
Power
Input
Input
Output
Power
Power
Type
1
Description
Power supply voltage for the device core and the inputs.
Non-inverting differential clock input. Compatible with LVPECL,
LVDS and CML signals.
Inverting differential clock input. Compatible with LVPECL, LVDS
and CML signals.
Bias voltage generator output. Use to bias the nCLK input in
single-ended input applications. V
BB
= V
CC
- 1.3V.
Ground supply voltage (GND) and ground return path. Connect to
board GND (0V).
Ground supply voltage (GND) and ground return path. Connect to
board GND (0V).
LVCMOS clock output QB. LVCMOS/LVTTL interface levels.
If this pin is disabled by connecting its power supply pin V
CCO_QB
to
GND, QB must be left open or connected to GND.
Positive supply voltage for the QB output. The QB output (if not
connected) can be disabled by connecting this pin to GND.
Positive supply voltage for the QA, nQA output. The QA, nQA output
(if not connected) can be disabled by connecting this pin to GND.
Differential clock output QA. LVPECL interface levels.
If this pin is disabled by connecting its power supply pins V
CCO_QA
to
GND, QA and nQA must be left open or connected to GND.
Differential clock output QA. LVPECL interface levels.
If this pin is disabled by connecting its power supply pins V
CCO_QA
to
GND, QA and nQA must be left open or connected to GND.
Positive supply voltage for the QA, nQA output. The QA, nQA output
(if not connected) can be disabled by connecting this pin to GND.
60k Pullup
Configuration pins. 3-Level interface. See
Table 3
for function and
Table 4D
for interface levels.
Ground supply voltage (GND) and ground return path. Connect to
board GND (0V).
60k Pullup
60k Pullup
Configuration pins. 3-Level interface. See
Table 3
for function and
Table 4D
for interface levels.
Configuration pin. 3-Level interface. See
Table 3
for function and
Table 4D
for interface levels.
7
QB
Output
8
9
10
V
CCO_QB
V
CCO_QA
QA
Power
Power
Output
11
12
13
14
15
16
nQA
V
CCO_QA
SEL0
GND
SEL1
EN
Output
Power
Input
Power
Input
Input
NOTE 1.
Pullup
refers to internal input resistors. See
Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
C
PD
R
PULLUP
R
OUT
Parameter
Input Capacitance
Power
Dissipation Capacitance
Input Pullup Resistor
LVCMOS
Output Resistance
V
CCO_QB
= 2.375V
V
CCO_QB
= 3.465V
42
Test Conditions
Minimum
Typical
2
5.4
60
38
28
78
Maximum
Units
pF
pF
k
©2018 Integrated Device Technology, Inc.
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January 21, 2018
8T73S1802 Datasheet
Principles Of Operation
Control Pins
The control input pins SEL0, SEL1 and EN are 3-level inputs with
internal 60k resistors that pull the input to the V
CC
level when left
open. Each input has three logic states: low (0), mid (V
CC
/2) and
high (1). Connect a control input to GND for achieving the low (0)
state. For the high (1) state, connect the input to V
CC
or leave the
input open. For the mid state, connect an external 60k resistor
from the input to GND. See
Table 4D
for the 3-state input min and
max levels.
Operation Modes
The device offers a many combinations of divider values and
output enable states. See
Table 3
for the supported modes.
Table 3. Operation Modes
1
Input
2 3 4
EN
0
SEL1
X
0
MID
MID
1
0
1
1
SEL0
X
0
MID
1
MID
1
0
0
1
0
1
Output Divider
QA (LVPECL)
Disabled
÷4
÷1
÷2
÷8
÷1
÷4
÷1
÷2
÷8
Disable
QB (LVCMOS)
Disabled
÷4
÷1
÷2
÷1
÷2
÷8
÷4
÷4
÷4
÷4
NOTE 1. In the default state (control input left open), QA is disabled and QB = ÷4.
NOTE 2. 0 = Low, MID = V
CC
/2, 1 = High; X = either 0, MID or 1.
NOTE 3. 0 = Low, MID = V
CC
/2, 1 = High; X = either 0, MID or 1.
NOTE 4. Unspecified EN, SEL1, SEL0 input logic states are reserved and should not be used.
©2018 Integrated Device Technology, Inc.
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January 21, 2018
8T73S1802 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC
Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, V
O
(LVCMOS)
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Maximum Junction Temperature, T
J_MAX
Storage Temperature, T
STG
ESD - Human Body Model
1
ESD - Charged Device Model
NOTE 1. According to JEDEC/JESD 22-A114/22-C101.
Rating
3.6V
-0.5V to V
CC
+ 0.5V
-0.5V to
V
CCO_QB
+ 0.5V
10mA
15mA
125°C
-65°C to 150°C
2000V
1500V
Electrical Characteristics
Table 4A. 3.3V Power Supply Characteristics, V
CC
= V
CCO_QA
= V
CCO_QB
= 3.0V to 3.465V, T
A
= -40°C to 85°C
Symbol
V
CC
V
CCO_QA,
V
CCO_QB
Parameter
Power Supply Voltage
Output Supply Voltage
All outputs enabled and terminated with
50 to V
CC
– 2V on LVPECL outputs and
10pF on LVCMOS output;
f = 800MHz for LVPECL outputs and
200MHz for LVCMOS, V
CC
= 3.3V
Outputs enabled, no load;
f = 800MHz for LVPECL outputs and
200MHz for LVCMOS, V
CC
= 3.465V
I
CCZ
Power Supply Current
1
Outputs Disabled, EN = 0,
f
IN
= 0Hz, V
CC
= 3.465V
All outputs enabled and terminated with
50 to V
CC
– 2V on LVPECL outputs and
10pF on LVCMOS output;
f = 800MHz for LVPECL outputs and
200MHz for LVCMOS
Test Conditions
Minimum
3.0
3.0
Typical
3.3
3.3
Maximum
3.465
3.465
Units
V
V
120
mA
I
CC
Power Supply Current
1
104
8.2
mA
mA
I
EE
Power Supply Current
92
109
mA
NOTE 1. I
CC
includes output current.
©2018 Integrated Device Technology, Inc.
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January 21, 2018
8T73S1802 Datasheet
Table 4B. 2.5V Power Supply Characteristics, V
CC
= V
CCO_QA
= V
CCO_QB
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
CC
Parameter
Power Supply Voltage
Test Conditions
Minimum
2.375
2.375
All outputs enabled and terminated with
50 to V
CC
– 2V on LVPECL outputs and
10pF on LVCMOS output;
f = 800MHz for LVPECL outputs and
200MHz for LVCMOS, V
CC
= 2.5V
Outputs enabled, no load;
f = 800MHz for LVPECL outputs and
200MHz for LVCMOS, V
CC
= 2.625V
I
CCZ
Power Supply Current
1
Outputs Disabled, EN = 0,
f
IN
= 0Hz, V
CC
= 2.625V
All outputs enabled and terminated with
50 to V
CC
– 2V on LVPECL outputs and
10pF on LVCMOS output;
f = 800MHz for LVPECL outputs and
200MHz for LVCMOS
Typical
2.5
2.5
Maximum
2.625
2.625
Units
V
V
V
CCO_QA,
Output Supply Voltage
V
CCO_QB
114
mA
I
CC
Power Supply Current
1
96
1.5
mA
mA
I
EE
Power Supply Current
85
99
mA
NOTE 1. I
CC
includes output current.
Table 4C. Differential Characteristics, V
CC
= V
CCO_QA
= 3.0V to 3.465V or 2.5V±5%, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
R
IN
V
BB
V
OH
V
OL
I
OZH
I
OZL
Parameter
Input
High Current
Input
Low Current
Input
Impedance
CLK, nCLK
CLK, nCLK
CLK, nCLK
I
BB
= -0.2mA
V
CC
– 1.4
V
CCO_QA
– 1.18
V
CCO_QA
– 1.98
V
CC
= V
CCO_QA_MAX
V
O
= V
CC
-0.8V
V
CC
= V
CCO_QA_MAX
V
O
= 0V
Test Conditions
V
CC
= V
IN
= V
CC_MAX
V
CC
= V
CC_MAX,
V
IN
= 0V
-10
22
V
CC
– 1.2
V
CCO_QA
– 0.81
V
CCO_QA
– 1.55
40
5
Minimum
Typical
Maximum
65
Units
µA
µA
k
V
V
V
µA
µA
Reference Voltage for Input
Bias
Output High Voltage
1
Output Low Voltage
1
Output Disabled Leakage
Current
2
Output Disabled Leakage
Current
2
NOTE 1. QA, nQA Outputs terminated with 50 to V
CC
– 2V.
NOTE 2. Maximum voltage applied to a disabled (high-impedance) output is 3.465V.
©2018 Integrated Device Technology, Inc.
5
January 21, 2018
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