dsPIC33EPXXXGS70X/80X
dsPIC33EPXXXGS70X/80X Family
Silicon Errata and Data Sheet Clarification
The dsPIC33EPXXXGS70X/80X family devices that
you have received conform functionally to the current
Device Data Sheet (DS70005258B), except for the
anomalies described in this document.
The silicon issues discussed in the following pages are
for silicon revisions with the Device and Revision IDs
listed in
Table 1.
The silicon issues are summarized in
Table 2.
The errata described in this document will be addressed
in future revisions of the dsPIC33EPXXXGS70X/80X
silicon.
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the issues
indicated in the last column of
Table 2
apply to the current silicon revision (A2).
For example, to identify the silicon revision level
using MPLAB IDE in conjunction with a hardware
debugger:
1.
2.
3.
4.
Using the appropriate interface, connect the
device to the hardware debugger.
Open an MPLAB IDE project.
Configure the MPLAB IDE project for the
appropriate device and hardware debugger.
Based on the version of MPLAB IDE you are
using, do one of the following:
a) For MPLAB IDE 8, select
Programmer >
Reconnect.
b) For MPLAB X IDE, select
Window > Dash-
board
and click the
Refresh Debug Tool
Status
icon (
).
Depending on the development tool used, the
part number
and
Device Revision ID value
appear in the
Output
window.
Note:
If you are unable to extract the silicon
revision level, please contact your local
Microchip sales office for assistance.
the
various
revisions are
5.
Data Sheet clarifications and corrections start on
page 14,
following the discussion of silicon issues.
The silicon revision level can be identified using the
current version of MPLAB
®
IDE and Microchip’s pro-
grammers, debuggers, and emulation tools, which are
available at the Microchip corporate web site
(www.microchip.com).
The
DEVREV
values
for
dsPIC33EPXXXGS70X/80X silicon
shown in
Table 1.
TABLE 1:
SILICON DEVREV VALUES
Device ID
(1)
Revision ID for
Silicon Revision
(2)
A2
Part Number
Device ID
(1)
Revision ID for
Silicon Revision
(2)
A2
dsPIC33EP128GS705
dsPIC33EP128GS706
dsPIC33EP128GS708
0x4001
dsPIC33EP128GS804
dsPIC33EP128GS805
dsPIC33EP128GS806
dsPIC33EP128GS808
0x6C30
0x6C12
0x6C13
0x6C50
0x6C70
0x6C52
0x6C53
0x4001
Part Number
dsPIC33EP64GS708
dsPIC33EP64GS804
dsPIC33EP64GS805
dsPIC33EP64GS806
dsPIC33EP64GS808
dsPIC33EP128GS702
dsPIC33EP128GS704
Note 1:
2:
0x6C03
0x6C40
0x6C60
0x6C42
0x6C43
0x6C11
0x6C10
The Device IDs (DEVID and DEVREV) are located at the last two implemented addresses of configuration mem-
ory space. They are shown in hexadecimal in the format “DEVID DEVREV”.
Refer to the
“dsPIC33EPXXXGS70X/80X Family Flash Programming Specification”
(DS70005256) for detailed
information on Device and Revision IDs for your specific device.
2017-2018 Microchip Technology Inc.
DS80000722D-page 1
dsPIC33EPXXXGS70X/80X
TABLE 2:
Module
CPU
SILICON ISSUE SUMMARY
Feature
Item
Number
1.
Issue Summary
When using the signed 32-by-16-bit division instruction,
div.sd,
the Overflow bit is not getting set when an overflow
occurs.
When Variable Interrupt Latency is selected (VAR =
1),
an
address error trap or incorrect application behavior may
occur.
PSV access, including Table Reads or Writes in the last
instruction of a
DO
loop, is not allowed.
Under specific conditions, multi-core ADC sampling
crosstalk noise might be present.
Parallel operation of the two oversampling filters results in
missing data writes to the lower priority Filter Data Result
register.
DNL is out of specification at the mid-code boundary in
Single-Ended mode.
The Transmit Shift Register Empty (TRMT) bit is unreliable
when there are back-to-back Break character transmissions.
The 7-bit address that matches the 10-bit upper address
value (111_10xx) can never be accepted, regardless of the
STRICT bit.
When data hold is enabled and software sends a NACK, a
slave interrupt is occurring after the 9th clock.
At start-up, the Idle state of the SDOx pin depends on the
MSB of the first data packet when the slave is configured for
Left/Right Justified mode.
In PCM/DSP mode, if the channel width is greater than data
width, the data loaded is not transmitted as per the loading
sequence.
In PCM/DSP mode, if the channel width is greater than data
width, the state of SDOx is latched to the LSB of the data
transmitted.
Single-stepping of the command sequence queue when
device is in Debug mode is not functional.
PTGADD
and
PTGCOPY
commands do not change the counter
limit values.
Software trigger (PTGSWT) is not cleared by hardware.
A glitch may be observed on the PWM pins when the PWM
module is enabled after assignment of pin ownership to the
PWM module.
Dead time between transitions of the PWMxH and PWMxL
outputs may not be asserted when Swap mode is disabled.
Changes to the PHASEx register after enabling the PWM
module may result in abnormal PWM switching waveforms.
When EIPU =
1,
Period register writes may produce
back-to-back pulses under certain conditions.
Affected
Revisions
(1)
A2
div.sd
X
CPU
Variable Interrupt
Latency
DO
Loop
ADC Sampling
Oversampling
Filter
DNL
Break
Character
Generation
Slave Mode
2.
X
CPU
ADC
ADC
3.
4.
5.
X
X
X
ADC
UART
6.
7.
X
X
I
2
C
8.
X
I
2
C
SPI
Slave Mode
Audio
9.
10.
X
X
SPI
Audio
11.
X
SPI
Audio
12.
X
PTG
PTG
PTG
PWM
Debug
PTGADD/
PTGCOPY
Software
Trigger
Module Enable
13.
14.
15.
16.
X
X
X
X
PWM
PWM
PWM
Note 1:
Center-Aligned
Complementary
Master Time
Base Mode
Push-Pull Mode
17.
18.
19.
X
X
X
Only those issues indicated in the last column apply to the current silicon revision.
DS80000722D-page 2
2017-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X
TABLE 2:
Module
PWM
SILICON ISSUE SUMMARY (CONTINUED)
Feature
Redundant/
Push-Pull
Output Mode
Trigger Compare
Match
5V Tolerant
5V Tolerant
APLL Lock
Slave Mode
Item
Number
20.
Issue Summary
Changing the duty cycle value from a non-zero value to zero
will produce a glitch pulse equal to 1 PWM clock.
The first PWM/ADC trigger event on a TRIGx/STRIGx match
may not occur under certain conditions.
Limited number of I/O pins support 5V operation.
Limit input current to I/O pins that support 5V operation.
The APLL lock bit is asserted directly after enabling the
APLL.
In Slave mode, false bus collision triggers are generated
during reception of a Stop bit when bus collision is enabled
(SBCDE =
1).
In Slave mode, the Bus Collision bit (BCL) cannot be cleared
when bus collision detection is enabled (SBCDE =
1).
Given a specific set of preconditions, when two or more data
Flash read instructions (via Program Space Visibility (PSV)
read or Table Read) are executed back-to-back, one or more
subsequent instructions will be misexecuted.
PWM generators may exhibit an incorrect phase relationship
when configured in Push-Pull mode.
Affected
Revisions
(1)
A2
X
PWM
I/O
I/O
Auxiliary
PLL
I
2
C
21.
22.
23.
24.
25.
X
X
X
X
X
I
2
C
CPU
Slave Mode
Data Flash
Reads
26.
27.
X
X
PWM
Note 1:
Push-Pull Mode
28.
X
Only those issues indicated in the last column apply to the current silicon revision.
2017-2018 Microchip Technology Inc.
DS80000722D-page 3
dsPIC33EPXXXGS70X/80X
Silicon Errata Issues
Note:
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A2).
3. Module: CPU
Table Write (TBLWTL,
TBLWTH)
instructions
cannot be the first or last instruction of a
DO
loop.
Work around
None.
Affected Silicon Revisions
A2
X
1. Module: CPU
When using the Signed 32-by-16-bit Division
instruction,
div.sd,
the Overflow bit may not
always get set when an overflow occurs.
This erratum only affects operations in which at
least one of the following conditions is true:
a)
b)
c)
Dividend and divisor differ in sign,
Dividend > 0x3FFFFFFF or
Dividend
0xC0000000.
4. Module: ADC
When using multiple ADC cores, if one of the
ADC cores completes conversion while other
ADC cores are still converting, the data in the
ADC cores which are converting may be
randomly corrupted.
Work around
Work around 1:
When using multiple ADC
cores, the ADC triggers are to be sufficiently
staggered in time to ensure that the end of the
conversion of one or more cores does not occur
during the conversion process of other cores.
Work around 2:
For simultaneous conversion
requirements, make sure the following
conditions are met:
1. All the ADC cores for simultaneous conversion
should have the same configurations.
2. Avoid shared ADC core conversion with any
of the dedicated ADC cores; they can be
sequential.
3. The trigger to initiate ADC conversion should
be from the same source and at the same
time.
Affected Silicon Revisions
A2
X
Work around
The application software must perform both the
following actions in order to handle possible
undetected overflow conditions:
a)
The value of the dividend must always be
constrained to be in the following range:
0xC0000000
Dividend
0x3FFFFFFF.
If the dividend and divisor differ in sign
(e.g., dividend is negative and divisor is
positive), then after executing the
div.sd
instruction or the compiler built-in function,
__builtin_divsd(),
inspect the sign of
the resultant quotient.
If the quotient is found to be a positive
number, then treat it as an overflow condition.
Affected Silicon Revisions
A2
X
b)
2. Module: CPU
An address error trap or incorrect application
behavior may occur if the variable exception
processing latency is enabled by setting the
VAR bit (CORCON<15> =
1).
Work around
Enable the Fixed Interrupt Latency mode by
clearing the VAR bit (CORCON<15> =
0).
Affected Silicon Revisions
A2
X
DS80000722D-page 4
2017-2018 Microchip Technology Inc.
dsPIC33EPXXXGS70X/80X
5. Module: ADC
If both oversampling filters are configured identi-
cally and have different input channel selections
(FLCHSEL<4:0> bits in the ADFLxCON register)
and the channels start conversion from the same
trigger source, then the lower priority filter result
will not be written to the Filter Output Data register.
Both data registers will contain the result from the
higher priority filter (i.e., ADFL0DAT).
Work around
Ensure oversampling filters have input channels
with different trigger sources and do not
complete conversions simultaneously.
Affected Silicon Revisions
A2
X
8. Module: I
2
C
In 7-Bit Addressing mode, the I
2
C module will
not respond to the 7-bit address that matches
with the upper byte of the 10-bit address.
If the 7-bit address matches with the upper byte
of the 10-bit address, the I
2
C module will send a
NACK, irrespective of the STRICT bit setting.
Work around
None.
Affected Silicon Revisions
A2
X
9. Module: I
2
C
In Slave mode with DHEN =
1
(Data Hold
Enable), if software sends a NACK, the slave
interrupt is asserted at the 9th falling edge of the
clock.
Work around
Software should ignore the slave interrupt that is
asserted after sending a NACK.
Affected Silicon Revisions
A2
X
6. Module: ADC
When the ADC SAR core is configured to
operate in Single-Ended mode, the core’s DNL
performance may be out of specification at the
mid-code boundary.
Work around
None.
Affected Silicon Revisions
A2
X
10. Module: SPI
When the SPI is a slave and configured for Left
Justified or Right Justified mode at start-up, the
Idle state of the SDOx pin will be configured by
the Most Significant bit (MSb) of the first data
packet loaded to the buffer.
For example:
If data loaded to the buffer is 0xA5A5 (where
MSb is ‘1’), then at start-up, the Idle state of
SDOx will be HIGH.
If data loaded to the buffer is 0x5A5A (where
MSb is ‘0’), then at start-up, the Idle state of
SDOx will be LOW.
Work around
None.
Affected Silicon Revisions
A2
X
7. Module: UART
The Transmit Shift Register Empty (TRMT) bit is
unreliable when there are back-to-back Break
character transmissions.
For back-to-back Break characters, the TRMT
bit may not reflect the actual status. If user soft-
ware is polling for this bit to be set, it may result
in dummy bytes getting transmitted instead of
Break characters.
Work around
Poll the UARTx Transmit Break bit, UTXBRK
(UxSTA<11>), to be cleared instead of the
TRMT bit (UxSTA<8>) to be set. The UTXBRK
status bit will be cleared after a Break character
transmission.
Affected Silicon Revisions
A2
X
2017-2018 Microchip Technology Inc.
DS80000722D-page 5
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