THC63LVDM83E_Rev.1.30_E
THC63LVDM83E
SMALL PACKAGE / 24Bit COLOR LVDS TRANSMITTER
General Description
The THC63LVDM83E transmitter is designed to
support pixel data transmission between Host and
Flat Panel Display up to 1080p/WUXGA resolutions.
The THC63LVDM83E converts 28bits of
CMOS/TTL data into LVDS (Low Voltage
Differential Signaling) data stream. The transmitter
can be programmed for rising edge or falling edge
clocks through a dedicated pin. At a transmit clock
frequency of 160MHz, 24bits of RGB data and 4bits
of timing and control data (HSYNC, VSYNC, DE,
CONT1) are transmitted at an effective rate of
1120Mbps per LVDS channel.
Features
½49pin
0.65mm pitch VFBGA Package
½Wide
dot clock range: 8-160MHz suited for
TV Signal : NTSC(12.27MHz) - 1080p(148.5MHz)
PC Signal : QVGA(8MHz) - WUXGA(154MHz)
½1.2V
to 3.3V CMOS inputs are supported.
½LVDS
swing is reducible by RS-pin to reduce EMI
and power consumption.
½PLL
requires no external components.
½On
chip jitter filtering.
½Spread
Spectrum Clock input tolerant.
½Power
down mode.
½Input
clock triggering edge is selectable by R/F-pin.
½Operates
from a Single 3.3V Supply and
110mW(typ.) at 75MHz.
Block Diagram
CMOS/TTL
INPUTS
TA0-6
TB0-6
TC0-6
TD0-6
7
7
7
7
THC63LVDM83E
DATA
(LVDS)
TA +/-
TB +/-
TC +/-
TD +/-
(56-1120Mbit/On Each
LVDS Channel)
PLL
TCLK +/-
CLOCK
(LVDS)
8-160MHz
TRANSMITTER
CLKIN
(8 to 160MHz)
R/F
/PDWN
RS
Copyright©2012 THine Electronics, Inc.
CMOS/TTL PARALLEL
TO SERIAL
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THine Electronics, Inc.
THC63LVDM83E_Rev.1.30_E
Pin Description
Pin Name
TA+, TA-
TB+, TB-
TC+, TC-
TD+, TD-
TCLK+,
TCLK-
TA0 ~ TA6
TB0 ~ TB6
TC0 ~ TC6
TD0 ~ TD6
/PDWN
RS
Pin #
B7, B6
C7, C6
D7, D6
F7, F6
E7, E6
A7,A6,A5,A4,A3,A2,A1
C2,D2,E2,F2,B1,C1,D1
E1,F1,G1,G2,G3,G4,G5
B5,B4,B3,B2,F3,F4,F5
G7
C5
Input
LV-CMOS
/TTL
Direction
Type
LVDS Data Out
Output
LVDS
LVDS Clock Out
Pixel Data Input
H : Normal operation
L : Power down (all outputs are Hi-Z)
LVDS swing mode, VREF select See Fig.5, 6
Description
R/F
CLKIN
VCC
GND
LVDS VCC
PLL VCC
E5
G6
C4
C3,D3,E3
D4,D5
E4
Power
---
LVDS
Small Swing
Swing
Input Support
VCC
350mV
N/A
0.6 ~ 1.4V
350mV
RS=VREF
GND
200mV
N/A
VREF is Input Reference Voltage
Input Clock Triggering Edge Select
H : Rising edge
L : Falling edge
Input Clock
Power Supply Pin for CMOS input and digital
circuit.
Ground Pins for Common.
Power Supply Pins for LVDS Outputs.
Power Supply Pin for PLL circuit.
RS
Copyright©2012 THine Electronics, Inc.
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THine Electronics, Inc.
THC63LVDM83E_Rev.1.30_E
Absolute Maximum Ratings
Parameter
Supply Voltage
LV-CMOS/TTL Input Voltage
LVDS Transmitter Output Voltage
Output Current
Junction Temperature
Storage Temperature
Reflow Peak Temperature
Reflow Peak Temperature Time
Maximum Power Dissipation @+25°C
Min
-0.3
-0.3
-0.3
-30
-55
Max
+4.0
VCC + 0.3
VCC + 0.3
30
+125
+125
+260
10
1.2
Units
V
V
V
mA
°C
°C
°C
sec
W
Recommended Operating Conditions
Symbol
Ta
Parameter
All Supply Voltage
Operating Ambient Temperature
Clock Frequency
Min
3.0
0
8
Typ
3.3
25
Max
3.6
+70
160
Units
V
°C
MHz
Copyright©2012 THine Electronics, Inc.
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THine Electronics, Inc.