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IDT71T75802S100BG

Description
512K X 36 ZBT SRAM, 4.2 ns, PBGA119
Categorystorage   
File Size234KB,26 Pages
ManufacturerIDT (Integrated Device Technology, Inc.)
Websitehttp://www.idt.com/
Download Datasheet Parametric View All

IDT71T75802S100BG Overview

512K X 36 ZBT SRAM, 4.2 ns, PBGA119

IDT71T75802S100BG Parametric

Parameter NameAttribute value
Number of functions1
Number of terminals119
Maximum operating temperature85 Cel
Minimum operating temperature-40 Cel
Maximum supply/operating voltage2.62 V
Minimum supply/operating voltage2.38 V
Rated supply voltage2.5 V
maximum access time4.2 ns
Processing package description14 X 22 MM, MS-028-AA, BGA-119
stateACTIVE
CraftsmanshipCMOS
packaging shapeRECTANGULAR
Package SizeGRID ARRAY
surface mountYes
Terminal formBALL
Terminal spacing1.27 mm
terminal coatingTIN LEAD
Terminal locationBOTTOM
Packaging MaterialsPLASTIC/EPOXY
Temperature levelINDUSTRIAL
memory width36
organize512K X 36
storage density1.89E7 deg
operating modeSYNCHRONOUS
Number of digits524288 words
Number of digits512K
Memory IC typeZBT SRAM
serial parallelPARALLEL
512K x 36, 1M x 18
2.5V Synchronous ZBT™ SRAMs
2.5V I/O, Burst Counter
Pipelined Outputs
IDT71T75602
IDT71T75802
Features
512K x 36, 1M x 18 memory configurations
Supports high performance system speed - 200 MHz
(3.2 ns Clock-to-Data Access)
ZBT
TM
Feature - No dead cycles between write and read
cycles
Internally synchronized output buffer enable eliminates the
need to control
OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW
1
-
BW
4
) control (May tie active)
Three chip enables for simple depth expansion
2.5V power supply (±5%)
2.5V I/O Supply (V
DDQ
)
Power down controlled by ZZ input
Boundary Scan JTAG Interface (IEEE 1149.1 Compliant)
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA)
Green parts available, see Ordering Information
Functional Block Diagram - 512K x 36
LBO
512Kx36 BIT
MEMORY ARRAY
Address
Address A [0:18]
CE1
,
CE2
,
CE2
R
/
W
CEN
ADV/LD
BW
x
D
Q
D
Q
Control
DI
DO
D
Input Register
Q
Clk
Control Logic
Mux
Sel
Clock
D
Output Register
Q
OE
Gate
Clk
TMS
TDI
TCK
TRST
(optional)
JTAG
TDO
Data I/O [0:31],
I/O P[1:4]
5313 drw 01
OCTOBER 2017
1
©2017 Integrated Device Technology, Inc.
DSC-5313/11
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