HM65W8512LTT-12V datasheet, PDF

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HM65W8512LTT-12V: DescriptionPseudo Static RAM, 512KX8, 120ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32; Categorystorage; File Size143KB，20 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HM65W8512LTT-12V Overview

Pseudo Static RAM, 512KX8, 120ns, CMOS, PDSO32, 0.400 INCH, PLASTIC, TSOP2-32

HM65W8512LTT-12V Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Hitachi （Renesas ）
Parts packaging code	TSOP2
package instruction	TSOP2, TSOP32,.46
Contacts	32
Reach Compliance Code	unknown
ECCN code	3A991.B.2.A
Is Samacsys	N
Maximum access time	120 ns
I/O type	COMMON
JESD-30 code	R-PDSO-G32
JESD-609 code	e0
length	20.95 mm
memory density	4194304 bit
Memory IC Type	PSEUDO STATIC RAM
memory width	8
Number of functions	1
Number of terminals	32
word count	524288 words
character code	512000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	512KX8
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	TSOP2
Encapsulate equivalent code	TSOP32,.46
Package shape	RECTANGULAR
Package form	SMALL OUTLINE, THIN PROFILE
Parallel/Serial	PARALLEL
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum standby current	0.000025 A
Minimum standby current	2 V
Maximum slew rate	0.05 mA
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	3 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
width	10.16 mm
Base Number Matches	1

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HM65W8512 Series

4 M PSRAM (512-kword

8-bit)

2 k Refresh

ADE-203-289C(Z)

Rev. 3.0

Nov. 1997

Description

The Hitachi HM65W8512 is a CMOS pseudo static RAM organized 512-kword

8bit. It realizes higher

density, higher performance and low power consumption by employing 0.8

µm

Hi-CMOS process

technology.

It offers low power data retention by self refresh mode. It also offers easy non multiplexed address

interface and easy refresh functions. HM65W8512 is suitable for handy systems which work with battery

back-up systems.

The device is packaged in a small 525-mil SOP (460-mil body SOP) or a 400 mil TSOP TYPE II.

Features

•

Single 3.3 V (±0.3V)

•

High speed



Access time

access time: 120/150 ns (max)



Cycle time

Random read/write cycle time:

190/230 ns (min)

•

Low power



Active: 100 mW (typ)



Standby: 85

µW

(typ)

•

Directly TTL/CMOS compatible

All inputs and outputs

•

Simple address configuration

Non multiplexed address

•

Refresh cycle



2048 refresh cycles: 32 ms

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Integral circuit diagram

Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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