Features
•
Power Management
– Supply Input from USB or 1x Disposal Battery (Alkaline, NimH, NiCd)
– Input Voltage Range: 0.9V to 1.8V
– 2.7V/2.9V/3.1V/3.3V - 100 mA Step-Up DC/DC Converter for Main Supply
– 2.7V to 3.5V (100mV step) - 150 mA LDO from USB supply
– 2.4V to 3.0V (200mV step) - 60 mA LDO for Analog Supply
– Reset Generator
– SPI Interface and Internal Programming Registers
– Dynamic Power Management
– Very Low Quiescent Current Operation
•
Stereo Audio DAC
– Programmable Stereo Audio DAC (16-bits, 18-bits or 20-bits)
– 93 dB SNR Playback Stereo Channels
– 32 Ohm/20 mW Stereo Headset Drivers with Master Volume and Mute Controls
– Stereo Line Level Input with Volume Control/Mute and Playback through the
Headset Driver
– Microphone Preamplifier
– Stereo, Mono and Reverse Stereo Mixer
– Left/Right Speaker Short-Circuit Detection Flag
– 8, 11.024, 16, 22.05, 24, 32, 44.1 and 48 kHz Sampling Rates
– 256x or 384xFs Master Clock Frequency
– I2S Serial Audio Interface
– Low Power Operation
•
Applications:
– Ideally Suited to Interface with Atmel’s AT8xC51SNDxC MP3 Microcontroller
– Portable Music Players, Digital Cameras, CD Players, Handheld GPS
Power
Management
and Analog
Companions
(PMAAC)
AT73C209
Audio and Power
Management
1. Description
The AT73C209 is a fully integrated, low cost, combined Stereo Audio DAC and Power
Management Circuit targeted for battery powered devices such as MP3 players in
“walkman” format or “mass storage” USB format.
The stereo DAC section is a complete high performance, stereo audio digital-to-ana-
log converter delivering a 93 dB dynamic range. It comprises a multibit sigma-delta
modulator with dither, continuous time analog filters and analog output drive circuitry.
This architecture provides a high insensitivity to clock jitter. The digital interpolation fil-
ter increases the sample rate by a factor of 8, using 3 linear phase half-band
cascaded filters, followed by a first order SINC interpolator with a sample-rate factor of
8. This filter eliminates the images of baseband audio, retaining only the image at 64x
the input sample rate, which is eliminated by the analog post filter. Optionally, a dither
signal can be added that reduces possible noise tones at the output. However, the
use of a multibit sigma-delta modulator provides extremely low noise tone energy.
Master clock is 256 or 384 times the input data rate, allowing multiple choice of input
data rate up to 48 kHz, including standard audio rates of 48, 44.1, 32, 16 and 8 kHz.
The DAC section also comprises volume and mute control and can be simultaneously
played back directly on the line outputs and through a 32-Ohms stereo headset.
6365A–PMAAC–12-Mar-08
The 32-Ohms pair of stereo-headset drivers also includes a LINEL and LINER channel-mixer
pair of stereo inputs.
Every DAC can be powered down separately via internal register control. Each single left or right
DAC can be directed in MONO mode to the stereo headset and line outputs while the other is
set in off mode.
In addition, a microphone preamplifier with a microphone bias switch is integrated, reducing
external ICs and saving board space.
The volume, mute, power down, de-emphasis controls and 16-bit, 18-bit and 20-bit audio for-
mats are digitally programmable via a 4-wire SPI bus and the digital audio data is provided
through a multi-format I2S interface.
The Power Management section can tolerate several types of input supply, such as:
• Battery: voltage is converted to 3.3V via a DC/DC step up converter using 1 external inductor,
1 schottky diode and a capacitor.
– Disposable AA or AAA size
– coin cell size, 1 cell, as low as 0.9V for alkaline
• USB: 5V VBUS supply from a USB connector or a Lithium-Ion battery
The Power Management section also includes a set of low dropout (LDO) voltage regulators
with different voltages to supply specific chip and analog requirements:
• LDO1 is designed to drive up to 150 mA from a USB port with 9-step programmable output
voltages: 2.7V, 2.8V, 2.9V, 3.0V, 3.1V, 3.2V, 3.3V, 3.4V, 3.5V. Default voltage is 3.4V and
represents the initial output voltage of LDO1 at start up. When RSTB is activated, the
external MCU can change the output voltage via the SPI serial interface. This LDO is
designed to supply the complete chip when the device is connected to a USB port.
• LDO2 is designed to drive up to 60 mA from LDO1 with 4-step programmable output
voltages: 2.4V, 2.6V, 2.8V, 3.0V with low noise and high PSRR. Default voltage is 3.0V and
represents the initial output voltage of LDO2 at start up. When RSTB is activated, the MCU
can change the output voltage via the SPI serial interface. This LDO is designed to supply the
internal analog section.
2
AT73C209
6365A–PMAAC–12-Mar-08
AT73C209
2. Block Diagram
Figure 2-1.
AT73C209 Functional Block Diagram
USB
IN
VREF
GNDB
VBG
Voltage
Reference
Integrated RC
Oscillator
LX
Band
Gap
SW1
DC-DC Step Up
3.3V / 100mA
FB
GNDSW1
GNDSW1S
ONOFF
Temperature
Monitoring Unit
MICOUT
MICINN
PGA
VCM
LDO1
3.4V / 150mA
Internal VCM
VBOOST
MICB
to LDO2
-36 to +12dB/
3dB step
Power Management
Logic
LDO2
3.0V / 60mA
Internal Analog Section
VANA
LINEL
PGA
-36 to +12dB/
3dB step
LINER
Status
Registers
AT73C209
SPI_DOUT
PGA
SPI
SPI_DIN
SPI_CLK
SPI_CSB
en_DAR
-6 to +6dB/ 3dB step
HSR
-46.5dB to 0dB
1.5dB step
32Ω
Driver
Σ
DAC
en_DAL
Serial Audio I/F
Right
Volume
Control
MCLK
RSTB
ITB
SDIN
LRFS
BCLK
-6 to +6dB/ 3dB step
HSL
Codec &
Mixer
-46.5dB to 0dB
1.5dB step
32Ω
Driver
Σ
DAC
Left
Volume
Control
INGND
AVDDHS
AGNDHS
3
6365A–PMAAC–12-Mar-08
3. Application Diagram
Figure 3-1.
Application Using One Cell Battery
L1
AC73C209
0.9V to 1.8V
C14
22µF
28
IN
LX
FB
25
D1
26
Battery
Cell
C1
22µF
DC-DC
GNDSW1
GNDSW1S
23
24
R1
100m
Ω
29
3.1V to 5.5V
USB
LDO1
LDO2
VBOOST
30
VANA
31
Push Button
27
C2
2.2µF
ONOFF
RSTB
ITB
22
5
LOGIC
CONTROL
MICOUT
8
TO ADC
C11
1µF
16
MICINN
INGND
VCM
7
17
C10
10µF
C9
1µF
32
MIC
VBG
C8
100nF
BANDGAP
6
R2
2.2KΩ
MICB
C12
10µF
C3
470nF
1
SPI_DIN
SPI_DOUT
SPI_CLK
SPI_CSB
LINEL
2
SERIAL
INTERFACE
3
SPI
LINER
15
Analog
Signal
Analog
Signal
4
14
C4
470nF
18
SDIN
HSR
BCLK
MCLK
LRFS
11
C5
100µF
RIGHT
HEADSET
19
DIGITAL
AUDIO
INTERFACE
20
I²S
CODEC &
MIXER
HSL
10
C6
100µF
LEFT
HEADSET
21
Connected to
VANA
12
AVDDHS
AGNDHS
13
GNDB
33
9
VREF
C13
1µF
C7*
1µF
C7* =~ C3 + C4
NOTE:
= DGND
= AGND
4
AT73C209
6365A–PMAAC–12-Mar-08
AT73C209
4. Components List
Table 4-1.
Reference
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
C12
C13
C14
D1
L1
R1
R2
SW1
Components List
Value
22 µF
2.2 µF / 10V
470 nF / 10V
470 nF / 10V
100 µF / 6.3V
100 µF / 6.3V
1 µF / 6.3V
100 nF / 16V
1 µF / 6.3V
10 µF / 6.3V
1 µF / 6.3V
10 µF / 6.3V
1 µF / 6.3V
22 µF / 4V
--
10 µH /550mA
0.1 Ohms
2.2 kOhms
Push Button
1%
5%
N/A
Techno
Tantalum
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Ceramic
Schottky
1812
--
0402
N/A
Series DSTMxx (APEM COMPONENTS) or equivalent
Size
Case A
0603
0402
0402
1210
1210
0402
0402
0402
0402
0402
0603
0402
0805
Manufacturer & Reference
(AVX) or equivalent
C1608X5R1A225MT (TDK) or GRM188R61A225 (Murata)
C1005X5R1A474KT (TDK) or GRM155F51A474 (Murata)
C1005X5R1A474KT (TDK) or GRM155F51A474 (Murata)
C3225X5R0J107MT (TDK) or GRM32ER60J107 (Murata)
C3225X5R0J107MT (TDK) or GRM32ER60J107 (Murata)
C1005X5R0J105KT (TDK) or GRM155R60J105 (Murata)
C1005X5R1C104KT (TDK) or GRM155F51C104 (Murata)
C1005X5R0J105KT (TDK) or GRM155R60J105 (Murata)
C1608X5R0J106MT (TDK) or GRM188R60G106 (Murata)
C1005X5R0J105KT (TDK) or GRM155R60J105 (Murata)
C1608X5R0J106MT (TDK) or GRM188R60G106 (Murata)
C1005X5R0J105KT (TDK) or GRM155R60J105 (Murata)
C2012X5R0J226MT (TDK) or GRM21BR60J226 (Murata)
MBRA120LT3 (ON Semiconductors) or equivalent
NLC453232T-100K-PF (TDK) or LQH43CN100K03 (Murata)
in 0805 Case or can be made by PCB tracks
5
6365A–PMAAC–12-Mar-08
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