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AT73C209-EK

Description
BOARD EVAL FOR AT73C209
CategoryDevelopment board/suite/development tools   
File Size1MB,63 Pages
ManufacturerMicrochip
Websitehttps://www.microchip.com
Download Datasheet Parametric Compare View All

AT73C209-EK Overview

BOARD EVAL FOR AT73C209

AT73C209-EK Parametric

Parameter NameAttribute value
typePower management
FunctionSpecial purpose: mobile phone
Embedded-
IC/parts usedAT73C209
Main attributes-
What's includedplate
Auxiliary properties-
Features
Power Management
– Supply Input from USB or 1x Disposal Battery (Alkaline, NimH, NiCd)
– Input Voltage Range: 0.9V to 1.8V
– 2.7V/2.9V/3.1V/3.3V - 100 mA Step-Up DC/DC Converter for Main Supply
– 2.7V to 3.5V (100mV step) - 150 mA LDO from USB supply
– 2.4V to 3.0V (200mV step) - 60 mA LDO for Analog Supply
– Reset Generator
– SPI Interface and Internal Programming Registers
– Dynamic Power Management
– Very Low Quiescent Current Operation
Stereo Audio DAC
– Programmable Stereo Audio DAC (16-bits, 18-bits or 20-bits)
– 93 dB SNR Playback Stereo Channels
– 32 Ohm/20 mW Stereo Headset Drivers with Master Volume and Mute Controls
– Stereo Line Level Input with Volume Control/Mute and Playback through the
Headset Driver
– Microphone Preamplifier
– Stereo, Mono and Reverse Stereo Mixer
– Left/Right Speaker Short-Circuit Detection Flag
– 8, 11.024, 16, 22.05, 24, 32, 44.1 and 48 kHz Sampling Rates
– 256x or 384xFs Master Clock Frequency
– I2S Serial Audio Interface
– Low Power Operation
Applications:
– Ideally Suited to Interface with Atmel’s AT8xC51SNDxC MP3 Microcontroller
– Portable Music Players, Digital Cameras, CD Players, Handheld GPS
Power
Management
and Analog
Companions
(PMAAC)
AT73C209
Audio and Power
Management
1. Description
The AT73C209 is a fully integrated, low cost, combined Stereo Audio DAC and Power
Management Circuit targeted for battery powered devices such as MP3 players in
“walkman” format or “mass storage” USB format.
The stereo DAC section is a complete high performance, stereo audio digital-to-ana-
log converter delivering a 93 dB dynamic range. It comprises a multibit sigma-delta
modulator with dither, continuous time analog filters and analog output drive circuitry.
This architecture provides a high insensitivity to clock jitter. The digital interpolation fil-
ter increases the sample rate by a factor of 8, using 3 linear phase half-band
cascaded filters, followed by a first order SINC interpolator with a sample-rate factor of
8. This filter eliminates the images of baseband audio, retaining only the image at 64x
the input sample rate, which is eliminated by the analog post filter. Optionally, a dither
signal can be added that reduces possible noise tones at the output. However, the
use of a multibit sigma-delta modulator provides extremely low noise tone energy.
Master clock is 256 or 384 times the input data rate, allowing multiple choice of input
data rate up to 48 kHz, including standard audio rates of 48, 44.1, 32, 16 and 8 kHz.
The DAC section also comprises volume and mute control and can be simultaneously
played back directly on the line outputs and through a 32-Ohms stereo headset.
6365A–PMAAC–12-Mar-08

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