3-Input, 3-Output Any-to-Any Line Card
PLL with Ultra-Low Jitter
ZL30151
Product Brief
August 2014
Features
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Input clocks
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Three inputs, two differential/CMOS, one CMOS
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Any input frequency from 1kHz to 650Hz
(1kHz to 300MHz for CMOS)
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Inputs continually monitored for activity and
frequency accuracy
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Automatic or manual reference switching
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Low-bandwidth DPLL
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Programmable bandwidth, 1Hz to 500Hz
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Attenuates jitter up to several UI
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Free-run or holdover on loss of all inputs
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Hitless reference switching
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High-resolution holdover averaging
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Digitally controlled phase adjustment
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Low-jitter Fractional-N APLL and 3 Outputs
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Any output frequency from <1Hz to 650MHz
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High-resolution fractional frequency conversion
with 0ppm error
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Easy-to-configure, encapsulated design
requires no external VCXO or loop filter
components
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Each output has independent dividers
•
Output jitter is typically 0.17 to 0.28ps RMS
(12kHz-20MHz integration band)
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Outputs are CML or 2xCMOS, can interface to
LVDS, LVPECL, HSTL, SSTL and HCSL
IC1P, IC1N
IC2P, IC2N
IC3P/GPIO3
Ordering Information
ZL30151LDG1
ZL30151LDF1
32 Pin QFN
32 Pin QFN
Matte Tin
Package size: 5 x 5 mm
-40
°
C to +85
°
C
Trays
Tape and Reel
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In 2xCMOS mode, the P and N pins can be
different frequencies (e.g. 125MHz and 25MHz)
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Per-output supply pin with CMOS output
voltages from 1.5V to 3.3V
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Precise output alignment circuitry and per-
output phase adjustment
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Per-output enable/disable and glitchless
start/stop (stop high or low)
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General Features
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Automatic self-configuration at power-up from
internal EEPROM; up to four configurations
pin-selectable
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Numerically controlled oscillator mode
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Zero-delay mode with external feedback
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SPI or I2C processor Interface
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Easy-to-use evaluation software
Applications
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•
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Telecom line cards for SONET/SDH, PDH,
Synchronous Etherenet, Fibre Channel
Broadcast video equipment
Frequency conversion and frequency synthesis in
a wide variety of equipment types
HSDIV1
HSDIV2
HSDIV3
Input Block
Divider,
Monitor,
Selector
Hitless Switching,
Jitter Filtering,
Holdover
DPLL
APLL
3.715-4.18GHz,
Fractional-N
HSDIV1
DIV1
DIV2
HSDIV2
(SPI or I2C Serial)
and HW Control and Status Pins
DIV3
OC1P, OC1N
VDDO1
OC2P, OC2N
VDDO2
OC3P, OC3N
VDDO3
Microprocessor Port
XA
XB
xtal
driver
×2
TEST/GPIO2
AC1/GPIO1
AC0/GPIO0
IC3/GPIO3
RSTN
IF0/CSN
SCL/SCLK
Figure 1 - Functional Block Diagram
1
Microsemi Corporation
Copyright 2014. Microsemi Corporation. All Rights Reserved.
SDA/MOSI
IF1/MISO
ZL30151
1. Application Examples
19.44M,
25M, etc.
Product Brief
From primary
and backup
timing functions
ZL30151
2x 156.25MHz differential
125MHz CMOS
25MHz CMOS
Input clock monitoring, hitless switching, frequency conversion,
and jitter attenuation if needed.
XO
Figure 2 - Telecom SyncE Line Card Application
27MHz or
74.25MHz or
74.1758MHz
ZL30151
27MHz or
74.25MHz or
74.1758MHz
Frequency conversion and optional jitter attenuation.
Figure 3 - Broadcast Video Frequency Conversion Application
2. Detailed Features
2.1
Input Block Features
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•
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Three input clocks, two differential or single-ended, one single-ended
Input clocks can be any frequency from 1kHz up to 650MHz (differential) or 300MHz (single-ended)
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN, wireless
Inputs constantly monitored by programmable activity monitors and frequency monitors
Fast activity monitor can disqualify the selected reference after a few missing clock cycles
Frequency measurement and monitoring with 1ppm resolution and accept/reject hysteresis
Optional input clock invalidation on GPIO assertion to react to LOS signals from PHYs
2.2
DPLL Features
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Very high-resolution DPLL architecture
State machine automatically transitions between free-run, locked, and holdover states
Revertive or nonrevertive reference selection algorithm
Programmable bandwidth from 1Hz to 500Hz
Programmable phase-slope limiting
Programmable frequency rate-of-change limiting
Programmable tracking range (i.e. hold-in range)
Truly hitless reference switching with <200ps output clock phase transient
Output phase adjustment in 10ps steps
High-resolution frequency and phase measurement
Fast detection of input clock failure and transition to holdover mode
Holdover frequency averaging with programmable averaging time and delay time
Better than 100ppb initial holdover accuracy
Very high-resolution fractional scaling (i.e. non-integer multiplication)
Any-to-any frequency conversion with 0ppm error
Two high-speed dividers (integers 4 to 15, half divides 4.5 to 7.5)
Easy-to-configure, completely encapsulated design requires no external VCXO or loop filter
components
Bypass mode supports system testing
2
Microsemi Corporation
2.3
APLL Features
ZL30151
2.4
Output Clock Features
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Product Brief
•
•
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•
•
•
•
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Three low-jitter output clocks
Each output can be one differential output or two CMOS outputs
Output clocks can be any frequency from 1Hz to 650MHz (250MHz max for CMOS and HSTL outputs)
Output jitter is typically 0.16 to 0.28ps RMS (12kHz to 20MHz)
In CMOS mode, an additional divider allows the OCxN pin to be an integer divisor of the OCxP pin
(Example 1: OC3P 125MHz, OC3N 25MHz. Example 2: OC2P 25MHz, OC2N 1Hz)
Outputs easily interface with CML, LVDS, LVPECL, HSTL, SSTL, HCSL and CMOS components
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN
Can produce clock frequencies for microprocessors, ASICs, FPGAs and other components
Can produce PCIe clocks (PCIe gen. 1, 2 and 3)
Sophisticated output-to-output phase alignment
Per-output phase adjustment with high resolution and unlimited range
Per-output enable/disable
Per-output glitchless start/stop (stop high or low)
2
2.5
General Features
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SPI or I C serial microprocessor interface
Automatic self-configuration at power-up from internal EEPROM memory; pin control to specify one of
four stored configurations
Numerically controlled oscillator (NCO) mode allows system software to steer DPLL frequency with
resolution better than 0.01ppb
Zero-delay buffer configuration using an external feedback path
Four general-purpose I/O pins each with many possible status and control options
Can operate as DPLL+APLL for jitter filtering and hitless switching or as APLL only
Local oscillator can be fundamental-mode crystal or low-cost XO
Internal compensation for local os
cill
ator frequency error
Simple, intuitive Windows-based graphical user interface
Supports all device features and register fields
Makes lab evaluation of the ZL30151 quick and easy
Generates configuration scripts to be stored in internal EEPROM
Generates full or partial configuration scripts to be run on a system processor
Works with or without a ZL30151 evaluation board
2.6
Evaluation Software
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3
Microsemi Corporation
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
Within the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
Email:
sales.support@microsemi.com
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
and systems solutions for: communications, defense and security, aerospace and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and
synchronization devices and precise time solutions, setting world’s standard for time; voice
processing devices; RF solutions; discrete components; security technologies and scalable
anti-tamper products; Power-over-Ethernet ICs and midspans; as well as customer design
capabilities and services. Microsemi is headquartered in Aliso Viejo, Calif. and has
approximately 3,400 employees globally. Learn more at
www.microsemi.com.
© 2014 Microsemi Corporation. All rights reserved. Microsemi and the Microsemi logo are trademarks of
Microsemi Corporation. All other trademarks and service marks are the property of their respective owners.
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