SiT8208
Ultra Performance Oscillator
The Smart Timing Choice
The Smart Timing Choice
Features
Applications
Any frequency between 1 and 80 MHz accurate to 6 decimal places
100% pin-to-pin drop-in replacement to quartz-based oscillators
Ultra low phase jitter: 0.5 ps (12 kHz to 20 MHz)
Frequency stability as low as ±10 PPM
Industrial or extended commercial temperature range
LVCMOS/LVTTL compatible output
Standard 4-pin packages: 2.5 x 2.0, 3.2 x 2.5, 5.0 x 3.2,
7.0 x 5.0 mm x mm
Instant samples with
Time Machine II
and
field programmable
oscillators
Outstanding silicon reliability of 2 FIT or 500 million hour MTBF
Pb-free, RoHS and REACH compliant
Ultra short lead time
SATA, SAS, Ethernet, PCI Express, video, WiFi
Computing, storage, networking, telecom, industrial control
Electrical Characteristics
[1]
Parameter
Output Frequency Range
Frequency Stability
Symbol
f
F_stab
Min.
1
-10
-20
-25
-50
First year Aging
10-year Aging
Operating Temperature Range
T_use
F_aging
-1.5
-5
-20
-40
Supply Voltage
Vdd
1.71
2.25
2.52
2.97
Current Consumption
OE Disable Current
Idd
I_OD
–
–
–
–
Standby Current
I_std
–
–
Duty Cycle
Rise/Fall Time
Output Voltage High
Output Voltage Low
Input Voltage High
Input Voltage Low
Input Pull-up Impedance
DC
Tr, Tf
VOH
VOL
VIH
VIL
Z_in
45
–
90%
–
70%
–
–
2
Typ.
–
–
–
–
–
–
–
–
–
1.8
2.5
2.8
3.3
31
29
–
–
–
–
–
1.2
–
–
–
–
100
–
Max.
80
+10
+20
+25
+50
+1.5
+5
+70
+85
1.89
2.75
3.08
3.63
33
31
31
30
70
10
55
2
–
10%
–
30%
250
–
Unit
MHz
PPM
PPM
PPM
PPM
PPM
PPM
°C
°C
V
V
V
V
mA
mA
mA
mA
A
A
%
ns
Vdd
Vdd
Vdd
Vdd
kΩ
MΩ
15 pF load, 10% - 90% Vdd
IOH = -6 mA, IOL = 6 mA, (Vdd = 3.3V, 2.8V, 2.5V)
IOH = -3 mA, IOL = 3 mA, (Vdd = 1.8V)
No load condition, f = 20 MHz, Vdd = 2.5V, 2.8V or 3.3V
No load condition, f = 20 MHz, Vdd = 1.8V
Vdd = 2.5V, 2.8V or 3.3V, OE = GND, output is Weakly Pulled
Down
Vdd = 1.8 V. OE = GND, output is Weakly Pulled Down
Vdd = 2.5V, 2.8V or 3.3V, ST = GND, output is Weakly Pulled
Down
Vdd = 1.8 V. ST = GND, output is Weakly Pulled Down
25°C
25°C
Extended Commercial
Industrial
Supply voltages between 2.5V and 3.3V can be supported.
Contact
SiTime
for additional information.
Inclusive of Initial tolerance at 25 °C, and variations over
operating temperature, rated power supply voltage and load
Condition
Frequency Range
Frequency Stability and Aging
Operating Temperature Range
Supply Voltage and Current Consumption
LVCMOS Output Characteristics
Input Characteristics
Pin 1, OE or ST
Pin 1, OE or ST
Pin 1, OE logic high or logic low, or ST logic high
Pin 1, ST logic low
Note:
1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.
SiTime Corporation
Rev. 1.02
990 Almanor Avenue
Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised June 24, 2013
SiT8208
Ultra Performance Oscillator
The Smart Timing Choice
The Smart Timing Choice
Electrical Characteristics
[1]
(Continued)
Parameter
Startup Time
OE Enable/Disable Time
Resume Time
Symbol
T_start
T_oe
T_resume
Min.
–
–
–
Typ.
7
–
6
Max.
10
150
10
Jitter
RMS Period Jitter
RMS Phase Jitter (random)
T_jitt
T_phj
–
–
–
1.5
2
0.5
2
3
1
ps
ps
ps
f = 75 MHz, Vdd = 1.8V
f = 10 MHz, Integration bandwidth = 12 kHz to 20 MHz
Unit
ms
ns
ms
Condition
Measured from the time Vdd reaches its rated minimum value
f = 80 MHz, For other frequencies, T_oe = 100 ns + 3 cycles
In standby mode, measured from the time ST pin crosses 50%
threshold. Refer to
Figure 5.
Startup and Resume Timing
Note:
1. All electrical specifications in the above table are specified with 15 pF output load and for all Vdd(s) unless otherwise stated.
Pin Configuration
Pin
Symbol
Output
Enable
1
OE/ ST
Standby
2
3
4
GND
OUT
VDD
Power
Output
Power
Open
[2]
:
Functionality
H or
specified frequency output
L: output is high impedance. Only output driver is disabled.
H or Open
[2]
: specified frequency output
L: output is low (weak pull down). Device goes to sleep mode. Supply
current reduces to I_std.
Electrical ground
[3]
Oscillator output
Power supply voltage
[3]
GND
2
3
Top View
OE/ST
1
4
VDD
OUT
Notes:
2. A pull-up resistor of <10 kΩ between OE/ ST pin and Vdd is recommended in high noise environment.
3. A capacitor of value 0.1 µF between Vdd and GND is recommended.
Absolute Maximum
Attempted operation outside the absolute maximum ratings of the part may cause permanent damage to the part. Actual perfor-
mance of the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Storage Temperature
VDD
Electrostatic Discharge
Soldering Temperature (follow standard Pb free soldering guidelines)
Junction Temperature
Min.
-65
-0.5
–
–
–
Max.
150
4
2000
260
150
Unit
°C
V
V
°C
°C
Thermal Consideration
Package
7050
5032
3225
2520
JA, 4 Layer Board
(°C/W)
191
97
109
117
JA, 2 Layer Board
(°C/W)
263
199
212
222
JC, Bottom
(°C/W)
30
24
27
26
Environmental Compliance
Parameter
Mechanical Shock
Mechanical Vibration
Temperature Cycle
Solderability
Moisture Sensitivity Level
Condition/Test Method
MIL-STD-883F, Method 2002
MIL-STD-883F, Method 2007
JESD22, Method A104
MIL-STD-883F, Method 2003
MSL1 @ 260°C
Rev. 1.02
Page 2 of 10
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SiT8208
Ultra Performance Oscillator
The Smart Timing Choice
The Smart Timing Choice
Phase Noise Plot
-100
-110
-120
-130
-140
-150
-160
-170
3
10
Integrated random phase jitter (RMS, 12kHz-5MHz): 0.52ps
Phase Noise (dBc/Hz)
10
4
10
Frequency Offset (Hz)
5
10
6
Figure 1. Phase Noise, 10 MHz, 3.3V, LVCMOS Output
Test Circuit and Waveform
Vdd
Vout
Test
Point
tr
4
Power
Supply
0.1µF
3
tf
90% Vdd
1
2
15pF
(including probe
and fixture
capacitance)
50%
10% Vdd
High Pulse
(TH)
Period
Low Pulse
(TL)
OE/ST Function
Vdd
1k
Figure 2. Test Circuit
Figure 3. Waveform
Notes:
4. Duty Cycle is computed as Duty Cycle = TH/Period.
5. SiT8208 supports the configurable duty cycle feature. For custom duty cycle at any given frequency, contact
SiTime.
Rev. 1.02
Page 3 of 10
www.sitime.com
SiT8208
Ultra Performance Oscillator
The Smart Timing Choice
The Smart Timing Choice
Timing Diagram
90% Vdd, 2.5/2,8/3.3V devices
Vdd
95% Vdd, 1.8V devices
Vdd
Pin 4 Voltage
NO Glitch first cycle
ST Voltage
50% Vdd
T_resume
CLK Output
T_start
CLK Output
T_start: Time to start from power-off
T_resume: Time to resume from ST
Figure 4. Startup Timing (OE/ST Mode)
u
Vdd
50% Vdd
T_OE
CLK Output
Figure 5. Standby Resume Timing (ST Mode Only)
OE Voltage
Vdd
OE Voltage
50% Vdd
CLK Output
T_OE
HZ
T_OE: Time to re-enable the clock output
T_OE: Time to put the output drive in High Z mode
Figure 6. OE Enable Timing (OE Mode Only)
Figure 7. OE Disable Timing (OE Mode Only)
Notes:
6. SiT8208 supports NO RUNT pulses and No glitches during startup or resume.
7. SiT8208 supports gated output which is accurate within rated frequency stability from the first cycle.
Rev. 1.02
Page 4 of 10
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SiT8208
Ultra Performance Oscillator
The Smart Timing Choice
The Smart Timing Choice
Performance Plots
3.3V
40.0
38.0
34.0
2.5V
1.8V
3.3V
3.00
2.50
2.00
1.50
1.00
0.50
0.00
10
2.5V
1.8V
Idd, mA
32.0
30.0
28.0
26.0
24.0
22.0
20.0
10
20
30
40
50
60
70
80
RMS Period jitter, ps
36.0
20
30
40
50
60
70
80
Frequency, MHz
Frequency, MHz
Figure 8. Idd vs Frequency
Figure 9. RMS Period Jitter vs Frequency
3.3V
55.0
54.0
2.5V
1.8V
1
0.9
2.5V
3.3V
1.8V
Duty cycle, %
52.0
51.0
50.0
49.0
48.0
47.0
46.0
45.0
10
20
30
40
50
60
70
80
RMS Phase jitter, ps
53.0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
10
20
30
40
50
60
70
80
Frequency, MHz
Frequency, MHz
Figure 10. Duty Cycle vs Frequency
Figure 11. RMS Phase Jitter vs Frequency
1.8V
35
33
31
29
27
25
-40
2.5V
3.3V
2.0
1.8V
2.5V
3.3V
Rise Time, ns
-20
0
20
40
60
80
1.5
Idd, mA
1.0
0.5
0.0
-40
-20
0
20
40
60
80
Temperature, °C
Temperature, °C
Figure 12. Idd vs Temperature, 10 MHz Output
Figure 13. Rise Time vs Temperature, 75 MHz Output
Note:
8. All plots are measured with 15 pF load at room temperature, unless otherwise stated.
Rev. 1.02
Page 5 of 10
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Analog electronics
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