INTEGRATED CIRCUITS
DATA SHEET
74LVT32374
3.3 V 32-bit edge-triggered D-type
flip-flop; 3-state
Product specification
Supersedes data of 2002 Mar 20
2004 Oct 15
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
FEATURES
•
32-bit edge-triggered flip-flop
•
3-state buffers
•
Output capability: +64 mA/−32 mA
•
TTL input and output switching levels
•
Input and output interface capability to systems at 5 V
supply
•
Bus-hold data inputs eliminate the need for external
pull-up resistors to hold unused inputs
•
Live insertion/extraction permitted
•
Power-up reset
•
Power-up 3-state
•
No bus current loading when output is tied to 5 V bus
•
Latch-up protection exceeds 500 mA in accordance with
JEDEC std 17
•
ESD protection exceeds 2000 V in accordance with
MIL STD 883 method 3015 and 200 V in accordance
with machine model.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
≤
2.5 ns.
SYMBOL
t
PHL
/t
PLH
C
I
C
O
I
CCZ
PARAMETER
propagation delay nCP to nQ
n
input capacitance
output capacitance
total supply current
CONDITIONS
C
L
= 50 pF; V
CC
= 3.3 V
V
I
= 0 V or 3.0 V
output disabled; V
CC
= 3.6 V
DESCRIPTION
74LVT32374
The 74LVT32374 is a high-performance BICMOS product
designed for V
CC
operation at 3.3 V.
The 74LVT32374 is a 32-bit edge-triggered D-type flip-flop
featuring non-inverting 3-state outputs. The device can be
used as four 8-bit flip-flops, or two 16-bit flip-flops or one
32-bit flip-flop. On the positive transition of the clock (CP),
the Q outputs of the flip-flop take on the logic levels set-up
at the D inputs.
TYPICAL
2.9
3
140
ns
pF
pF
µA
UNIT
outputs disabled; V
O
= 0 V or 3.0 V 9
2004 Oct 15
2
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
FUNCTION TABLE
See note 1.
INPUT
OPERATING MODE
nOE
Load and read register
Hold
Disable outputs
L
L
L
M
74LVT32374
nCP
↑
↑
nD
n
l
h
X
X
INTERNAL
REGISTER
L
H
NC
NC
OUTPUT
nQ
n
L
H
NC
Z
H
↑
H
Note
1. H = HIGH voltage level;
nD
n
nD
n
Z
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW OE transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW OE transition;
NC = not connected;
X = don’t care;
Z = high-impedance OFF-state;
↑
= LOW-to-HIGH CP transition;
= not a LOW-to-HIGH CP transition.
ORDERING INFORMATION
TYPE NUMBER
74LVT32374EC
PINNING
SYMBOL
nD
n
nCP
nQ
n
GND
nOE
V
CC
data input
clock input
flip-flop output
ground (0 V)
output enable input (active LOW)
supply voltage
DESCRIPTION
TEMPERATURE
RANGE
−40 °C
to +85
°C
PACKAGE
PINS
96
PACKAGE
LFBGA96
MATERIAL
plastic
CODE
SOT536-1
2004 Oct 15
3
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
handbook, full pagewidth
MNA497
6
5
4
3
2
1
1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D7 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D6
1D0 1D2 1D4 1D6 2D0 2D2 2D4 2D6 3D0 3D2 3D4 3D6 4D0 4D2 4D4 4D7
1CP GND VCC GND GND VCC GND 2CP 3CP GND VCC GND GND VCC GND 4CP
1OE GND VCC GND GND VCC GND 2OE 3OE GND VCC GND GND VCC GND 4OE
1Q0 1Q2 1Q4 1Q6 2Q0 2Q2 2Q4 2Q6 3Q0 3Q2 3Q4 3Q6 4Q0 4Q2 4Q4 4Q7
1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q7 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Fig.1 Pin configuration.
handbook, full pagewidth
1D0
D
CP
Q
1Q0
2D0
D
CP
Q
2Q0
FF 1
FF 9
1CP
1OE
to 7 other channels
2CP
2OE
to 7 other channels
3D0
D
CP
Q
3Q0
4D0
D
CP
Q
4Q0
FF 17
FF 25
3CP
3OE
to 7 other channels
4CP
4OE
to 7 other channels
MNA498
Fig.2 Logic symbol.
2004 Oct 15
4
Philips Semiconductors
Product specification
3.3 V 32-bit edge-triggered D-type flip-flop;
3-state
74LVT32374
handbook, halfpage
VCC
handbook, halfpage
VCC
27
Ω
output
27
Ω
data
input
to internal circuit
MNA473
MNA676
Fig.3 Schematic of each output.
Fig.4 Bus hold circuit.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆V
T
amb
P
tot
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 70
°C
the value of P
tot
derates linearly with 1.8 mW/K.
PARAMETER
supply voltage
input voltage
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
input transition rise or fall times
ambient temperature
power dissipation per package
note 2
outputs enabled
note 1
CONDITIONS
0
2.0
−
−
−
current duty cycle
≤
50 %; f
≥
1 kHz
−
−
−40
−
MIN.
2.7
MAX.
+3.6
5.5
−
0.8
−32
32
64
10
+85
1000
V
V
V
V
mA
mA
mA
ns/V
°C
mW
UNIT
2004 Oct 15
5
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